Assembly Language

Assembly Language

Chapter 8 I/O I/O: Connecting to Outside World So far, weve learned how to: compute with values in registers load data from memory to registers store data from registers to memory But where does data in memory come from? And how does data get out of the system so that humans can use it? 8-2 I/O: Connecting to the Outside World Types of I/O devices characterized by: behavior: input, output, storage input: keyboard, mouse, network interface output: monitor, printer, network interface storage: disk, CD, DVD, flash drive

data rate: how fast can data be transferred? keyboard: 100 bytes/sec disk: ~10 GB/s network: 10 Mb/s - 1 Gb/s 8-3 I/O Controller Control Register CPU tells device what to do write to control register Status Registers CPU checks whether task is done read status register Data Register CPU transfers data to/from device Status CPU

Control Graphics Controller Electronics display Device electronicsOutput Data performs actual operation pixels to screen, bits to/from disk, characters from keyboard 8-4 Programming Interface How do we read/write to/from device registers? Memory-mapped vs. special instructions How do we control the timing of read/write? Asynchronous vs. synchronous

How do we find out when unexpected events occur? CPU (polling) vs. device (interrupts) 8-5 Memory-Mapped I/O (I/O masquerading as memory) Memory-mapped mapa memory address to each device register use data movement instructions (LD/ST) read/write to registers Location I/O Register Function xFE00

Keyboard Status Reg (KBSR) Bit [15] is one when keyboard has received a new character. xFE02 Keyboard Data Reg (KBDR) Bits [7:0] contain the last character typed on keyboard. xFE04 Display Status Register (DSR) Bit [15] is one when device ready to display another char on screen. xFE06

Display Data Register (DDR) Character written to bits [7:0] will be displayed on screen. 8-6 Memory-Mapped I/O How do we: Read from the keyboard (perform input)? Write to the screen (perform output)? 8-7 Special I/O Instructions Instructions designate opcode(s) for I/O register and operation encoded in instruction

This is fictitious!! Not LC-3!!! I/O: Device: Function: 1101 Keyboard = 3 0: Check to see if device has data If data, put 1 in R0 Monitor = 4 1: Read data from device into R0

Mouse = 7 2: Check to see if device is ready for data. If so, put 0 into R0 USB Port = 9 3: Write data from R0 to device 8-8 Special I/O Instructions How do we: Read from the keyboard (perform input)? Write to the screen (perform output)? 8-9 Comparison

Memory mapped I/O Advantages: Disadvantages: Special I/O instructions Advantages: Disadvantages: 8-10 Transfer Timing I/O events generally happen much slower than CPU cycles. Synchronous data supplied at a fixed, predictable rate CPU reads/writes every X cycles Asynchronous

data rate less predictable CPU must synchronize with device, so that it doesnt miss data or write too quickly 8-11 Transfer Control Who determines when the next data transfer occurs? Polling CPU keeps checking status register until new data arrives OR device ready for next data Are we there yet? Are we there yet? Are we there yet? Interrupts Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. Wake me when we get there. 8-12

LC-3 Memory-mapped I/O Location I/O Register Function xFE00 Keyboard Status Reg (KBSR) Bit [15] is one when keyboard has received a new character. xFE02 Keyboard Data Reg (KBDR) Bits [7:0] contain the last character

typed on keyboard. xFE04 Display Status Register (DSR) Bit [15] is one when device ready to display another char on screen. xFE06 Display Data Register (DDR) Character written to bits [7:0] will be displayed on screen. Asynchronous devices synchronized through status registers Polling and Interrupts

the details of interrupts will be discussed in Chapter 10 8-13 Input from Keyboard When a character is typed: its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero) the ready bit (KBSR[15]) is set to one keyboard is disabled -- any typed characters will be ignored 15 8 7 keyboard data 0 KBDR 1514

ready bit 0 KBSR When KBDR is read: KBSR[15] is set to zero keyboard is enabled 8-14 Basic Polling Input Routine NO Polling new char? YES

read character 8-15 Output to Monitor When Monitor is ready to display another character: the ready bit (DSR[15]) is set to one 15 8 7 output data 0 DDR 1514

ready bit 0 DSR When data is written to Display Data Register: DSR[15] is set to zero (to indicate its busy) character in DDR[7:0] is displayed DSR[15] is set to one when displaying is complete 8-16 Basic Polling Output Routine NO Polling screen

ready? YES write character 8-17 Putting it all together: Keyboard Echo Routine Usually, input character is also printed to screen. User gets feedback on character typed and knows its ok to type the next character. POLL1 POLL2 LDI BRzp LDI LDI

BRzp STI R0, KBSR POLL1 R0, KBDR R1, DSR POLL2 R0, DDR NO YES read character ... KBSR KBDR

DSR DDR .FILL .FILL .FILL .FILL xFE00 xFE02 xFE04 xFE06 new char? NO screen ready?

YES write character 8-18 Problems with Polling Polling consumes a lot of cycles, especially for rare events these cycles can be used for more computation. Example: Process previous input while collecting current input. Solution: Have hardware, not software, detect events. 8-19 Interrupt-Driven I/O External device can:

(1) Force currently executing program to stop; (2) Have the processor satisfy the devices needs; and (3) Resume the stopped program as if nothing happened. 8-20 Interrupt-Driven I/O To implement an interrupt mechanism, we need: A way for the I/O device to signal the CPU that an interesting event has occurred. A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program. Generating Signal Software sets "interrupt enable" bit in device register. When ready bit is set and IE bit is set, interrupt is signaled. interrupt enable bit ready bit

1514 13 0 KBSR interrupt signal to processor 8-21 Priority Every instruction executes at a stated level of urgency. LC-3: 8 priority levels (PL0-PL7) Example: Payroll program runs at PL0. Nuclear power correction program runs at PL6. Its OK for PL6 device to interrupt PL0 program, but not the other way around. Priority encoder selects highest-priority device, compares to current processor priority level,

and generates interrupt signal if appropriate. 8-22 Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases. If not set, continues with next instruction. If set, transfers control to interrupt service routine. F NO Transfer to ISR YES interrupt signal? D EA OP

EX More details in Chapter 10. S 8-23 Review Questions What is the danger of not testing the DSR before writing data to the screen? What is the danger of not testing the KBSR before reading data from the keyboard? What is the advantage of using LDI/STI for accessing device registers? 8-24

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