Chapter 5

Chapter 5

College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 12 CPU Design & Programming 1 Unit 12: CPU Design & Programming Overview Simple Computer Architecture Instruction Set Architecture (ISA) Storage Resources

Instruction Formats Instruction Specifications Single-Cycle Hardwired Control Unit Assembly and machine Chapter-8 languages M. Morris Mano, Charles R. Kime and Tom Martin, Logic and Computer Design Fundamentals, Global (5th) Edition, Pearson Education Limited, 2016. ISBN: 9781292096124 An overview of CPU design We can divide the design of our CPU into three parts: The datapath does all of the actual data processing (Unit-11). An instruction set is the programmers interface to CPU. A control unit uses the programmers instructions to tell the datapath what to do.

3 Simple Computer Architecture A computer is controlled by a series of instructions. Instructions are binary words that are used to determine both the datapath processing and the control behavior. A program is a collection of instructions that are used to accomplish some task(s). A program counter (PC) is used to keep track of the address of the next instruction in memory. The PC has counting logic, as well as parallel load and other logic to permit changes in the instruction sequence. 4 Simple Computer Architecture

Changes in the instruction sequence can be either conditional or unconditional. Instructions are executed by activating the necessary microoperations to perform the specified task. Note that the computer uses programmable control, but we will use a hardwired control unit to actually implement the programmable control. 5 Instruction Set Architecture (ISA) The instruction set architecture (ISA): a comprehensive description of the instructions a computer can execute. The ISA has three major components Storage Resources

Instruction Formats Instruction Specification 6 Storage Resources resources available for storing information Register file Program counter (PC) Instruction memory (program memory) Data memory

Program counter (PC) Instruction memory 215 x 16 Register file 8 x16 Data memory 215 x 16

Henry Hexmoor 7 FIGURE 8-13 Storage Resource Diagram for a Simple Computer Instruction Formats Instructions are divided into bit groupings called fields. Each field will contain a specific part of the instruction. Operation code (opcode) The opcode field determines what the actual operation will be. An n-bit opcode can specify up to 2n different operations. Operand(s) Registers

Addresses of Operands Constant data Operands may be specified implicitly as well. 8 Instruction Formats -1 Register: The source(s) and destination of an instruction can all be registers. The source registers are read and the new information is written to the destination register. All registers are explicitly identified (usually). Instruction Formats - 2 Immediate operands: data constants are contained within the instruction. Note that only three bits of data can be specified

here, so It must be extended to the register length by zero-fill or sign-extension. Clever encodings enable wider immediates RR format, RI format, B format 10 Instruction Formats - 3 Jump and Branch: Changes in program flow are caused by jump or branch instructions, affecting only the PC. 1. Can load the PC from source SA. 2. Can add the sign-extended 6-bit offset (AD) to the PC. 3. Can be either unconditional, or conditional based on some flag value (i.e. Z, N, C, V).

11 Instruction Specifications The instruction specifications describe in detail each instruction the system can execute. A mnemonic is written by the programmer to represent the opcode in text. assembler generates the actual binary instruction. Not every instruction sets every flag Refer to Table 8-8 12 ISA: Instruction Specifications The specifications provide: The name of the instruction

The instruction's opcode A shorthand name for the opcode called a mnemonic A specification for the instruction format A register transfer description of the instruction, and A listing of the status bits that are meaningful during an instruction's execution (not used in the architectures defined in this chapter) 13 ISA: Instruction Specifications Here we have arithmetic, logic and shift instruction sets correspond to micro-operations discussed in Unit 8-11. The opcode (7 bit) and FS (4 bit) have one-to-one correspondence first three bits of an opcode are 000. RTL instruction (in description) is written in a slightly different way. For example, R[DR] <- R[SA] is a RTL instruction where DR and SA are destination and source register addresses respectively.

ISA: Instruction Specifications (continued) These are additional instructions having no corresponding micro-operations for them first three bits have non-zero values. For instruction LDI, RTL is R[DR] <- zf OP where zf means zero filled and OP is a 3 bit constant (that is used for the simple computer). In description of BRZ and BRN, se mean sign extended. This is done to make it 16 bit because the RAM has 216 16 configuration (refer to slide 8, figure 8-13). ISA: Memory Representation Table 8-9 shows Instructions and data, in binary, are placed in memory. Here, we assume that we have a program (in machine language) in the RAM and we show instructions at locations 25, 35, 45, and 55 (as examples). Corresponding assembly codes for four instructions are as follows. 25: SUB R1, R2, R3

35: ST (R4), R5 [suppose R4=70, R5=80] 45: ADI R2, R7, 3 55: BRZ R6, AD [suppose AD(left)=101, AD(right)=100, se AD = 1111111111101100 = -20] Block diagram of a processor Program Control signals Control Unit Status signals

Datapath The control unit connects programs with the datapath. In real computers, the datapath actions are determined by the program thats loaded and running It converts program instructions into control words for the datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD. It executes program instructions in the correct sequence. It generates the constant input for the datapath. The datapath also sends information back to the control unit. For instance, the ALU status bits V, C, N, Z can be inspected by branch instructions to alter a programs control flow. 17 Single-Cycle Hardwired Control In single-cycle hardwired control, the PC is

updated on each clock cycle. Each instruction is completed in a single cycle. The PC is used to select a word from the instruction memory, which is driven to the instruction decoder. The instruction decoder then provides the control word to the datapath to activate the desired functionality, and determines how the PC is updated. 18 The concatenated offset field is The instruction sign-extended for PC-relative decoder maps the

addressing. The constant instruction word to field is zero- a control word. PL if 0, the PC increments, otherwise filled and made IR

available to the the update is datapath controlled by JB JB if 0, do conditional branch, otherwise do unconditional jump Control Unit BC if 0, do BRZ,

otherwise do BRN Chapter 8 19 Instruction Decoder destination Source A Source B Chapter 8 20 Instruction Decoder Control-word fields DA, AA, and BA are equal to the instruction fields DR, SA, and SB, respectively Control field BC for selection of the branch condition status bits is taken directly from the last bit of Opcode.

The remaining control-word fields: MB, MD, RW, and MW There are two added bits for the control of the PC: PL and JB 21 Sample Programs Example Program: Assume address 248 in data memory containing 2, and location 249 contains 83. Evaluation of arithmetic expression 83 - (2 + 3) and place the result in location 250. LDI R3, 248 Load address 248 in R3 LD R1, (R3) Load R1 with contents of location 248 in memory (R1 becomes = 2)

ADI R1, R1, 3 Add 3 to R1 (R1 becomes =5) INC R3, R3 Increment the contents of R3 (R3 becomes = 249) LD R2, (R3) Load R2 with contents of location 249 in memory (R2 becomes = 83) SUB R2, R2, R1 Subtract contents of R1 from contents of R2 (R2 becomes INC R3, R3 Increment the contents of R3 (R3 = 250)

ST (R3), R2 Store R2 in memory location 250 (M[250] = 78) = 78) 22 Single-Cycle Computer Issues Complex operations Only combinational logic can be used in data transformation no sequential logic E.g. no multiplier Unified memory If program and data are in one memory,

how can you simultaneously access the same memory for an instruction and a data operand? Worst-case delay Chapter 10 23 Programming and CPUs Programs written in a high-level language like C++ must be compiled to produce an executable program. The result is a CPU-specific machine language program. This can be loaded into memory and

executed by the processor. CSC 220 focuses on stuff below the dotted blue line, but machine language serves as the interface between hardware and software. Machine language instructions are sequences of bits in a specific order. To make things simpler, people typically use assembly language. Example assemblers for Intel x86 processor: NASM, YASM, MASM High-level program Compiler Executable file Control Unit

Software Hardware Control words Datapath 24

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