CSCE 612: VLSI System Design - Computer Science & E

CSCE 612: VLSI System Design - Computer Science & E

Chapter 5 Large and Fast: Exploiting Memory Hierarchy Grades Exams 1 and 2 Grade Exam 2 Exam 1 Ave 77.5% 75.8% Median 81.0% 75.4%

Grade Exam 2 Exam 1 90-100 14 15 80-89 10 6 70-79 7

4 60-69 4 7 < 60 8 11 CSCE 212 2 Final Grades Grade Count A

12 B+ 5 B 3 C+ 7 C 3 D+ 5 D

2 F 6 Count CS CE EE Count 17 7 18

Final Score Ave. 80.1% 80.1% 74.9% Does not include grad/no shows 5 grades > 96% (11.2%) Overall ave. =79.2% CSCE 212 3 Principle of Locality Programs access a small proportion of their address space at any time Temporal locality

Items accessed recently are likely to be accessed again soon e.g., instructions in a loop, induction variables Spatial locality Items near those accessed recently are likely to be accessed soon E.g., sequential instruction access, array data Taking Advantage of Locality Memory hierarchy Store everything on disk Copy recently accessed (and nearby) items from disk to smaller DRAM memory Main memory Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory Cache memory attached to CPU Memory Hierarchy Levels Block (aka line): unit of copying May be multiple words

If accessed data is present in upper level Hit: access satisfied by upper level Hit ratio: hits/accesses If accessed data is absent Miss: block copied from lower level Time taken: miss penalty Miss ratio: misses/accesses = 1 hit ratio Then accessed data supplied from upper level Chapter 5 Large and Fast: Exploiting Memory Hierarchy 6 Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM) 50ns 70ns, $20 $75 per GB

Magnetic disk 5ms 20ms, $0.20 $2 per GB Ideal memory Access time of SRAM Capacity and cost/GB of disk Memory Hierarchy Desk metaphor (1 inch/cycle): CPU registers: index card L1 cache: 1 page, 1 inch away L2 cache: 31 pages, 3 inches away L3 cache: 125 pages, 16 inches away Main memory: 200 books, 5 feet away Disk: 60,000 books, 950 miles away

Tertiary storage (tapes): 100 million books, 100 million miles CSCE 212 8 DRAM Technology Data stored as a charge in a capacitor Single transistor used to access the charge Must periodically be refreshed Read contents and write back Performed on a DRAM row Advanced DRAM Organization Bits in a DRAM are organized as a rectangular array DRAM accesses an entire row Burst mode: supply successive words from a row with reduced latency Double data rate (DDR) DRAM Transfer on rising and falling clock edges Quad data rate (QDR) DRAM Separate DDR inputs and outputs

DRAM Generations Year Capacity $/GB 1980 64Kbit $1500000 1983 256Kbit $500000 1985 1Mbit

$200000 1989 4Mbit $50000 1992 16Mbit $15000 1996 64Mbit $10000 1998 128Mbit

$4000 2000 256Mbit $1000 2004 512Mbit $250 2007 1Gbit $50 300 250

200 Trac Tcac 150 100 50 0 '80 '83 '85 '89 '92 '96 '98 '00 '04 '07 DRAM Performance Factors Row buffer Allows several words to be read and refreshed in parallel Synchronous DRAM Allows for consecutive accesses in bursts without needing to send each address Improves bandwidth DRAM banking Allows simultaneous access to multiple DRAMs Improves bandwidth

Increasing Memory Bandwidth 4-word wide memory Miss penalty = 1 + 15 + 1 = 17 bus cycles Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle 4-bank interleaved memory Miss penalty = 1 + 15 + 41 = 20 bus cycles Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle Flash Storage Nonvolatile semiconductor storage 100 1000 faster than disk

Smaller, lower power, more robust But more $/GB (between disk and DRAM) Chapter 5 Large and Fast: Exploiting Memory Hierarchy 14 Flash Types NOR flash: bit cell like a NOR gate Random read/write access Used for instruction memory in embedded systems NAND flash: bit cell like a NAND gate Denser (bits/area), but block-at-a-time access Cheaper per GB Used for USB keys, media storage, Flash bits wears out after 1000s of accesses Not suitable for direct RAM or disk replacement Wear leveling: remap data to less used blocks Chapter 5 Large and Fast: Exploiting Memory Hierarchy 15 Disk Storage Nonvolatile, rotating magnetic storage

Chapter 5 Large and Fast: Exploiting Memory Hierarchy 16 Disk Sectors and Access Each sector records Sector ID Data (512 bytes, 4096 bytes proposed) Error correcting code (ECC) Used to hide defects and recording errors Synchronization fields and gaps Access to a sector involves Queuing delay if other accesses are pending Seek: move the heads Rotational latency Data transfer

Controller overhead Chapter 5 Large and Fast: Exploiting Memory Hierarchy 17 Disk Access Example Given 512B sector, 15,000rpm, 4ms average seek time, 100MB/s transfer rate, 0.2ms controller overhead, idle disk Average read time = queuing delay + seek + rotational latency + transfer time + controller delay 4ms seek time + / (15,000/60) = 2ms rotational latency + 512 / 100MB/s = 0.005ms transfer time + 0.2ms controller delay = 6.2ms If actual average seek time is 1ms Average read time = 3.2ms

Chapter 5 Large and Fast: Exploiting Memory Hierarchy 18 Example A program repeatedly performs the following three-step process: read in a 4 KB block of data from disk, do some processing on that data, and write out the result as another 4 KB block elsewhere on the disk. Each block is contiguous, located on a random track, and doesnt span multiple tracks. The disk rotates at 10,000 RPM, has an average seek time of 8 ms, and has a transfer rate of 50 MB/sec. The controller overhead is 2 ms. No other programs are using the disk or processor, and there is no overlapping of disk operation with processing. The processing step takes 20 million clock cycles, and the clock rate is 5 GHz. What is the overall speed of the system in blocks processed per second? CSCE 212 19 Cache Memory Cache memory The level of the memory hierarchy closest to the CPU Given accesses X1, , Xn1, Xn

How do we know if the data is present? Where do we look? Direct Mapped Cache Location determined by address Direct mapped: only one choice (Block address) modulo (#Blocks in cache) #Blocks is a power of 2 Use low-order address bits

Tags and Valid Bits How do we know which particular block is stored in a cache location? Store block address as well as the data Actually, only need the high-order bits Called the tag What if there is no data in a location? Valid bit: 1 = present, 0 = not present Initially 0 Cache Example 8-blocks, 1 word/block, direct mapped Initial state Index V 000 N 001

N 010 N 011 N 100 N 101 N 110 N

111 N Tag Data Cache Example Word addr Binary addr Hit/miss Cache block 22 10 110 Miss

110 Index V 000 N 001 N 010 N 011 N 100

N 101 N 110 Y 111 N Tag Data 10 Mem[10110]

Cache Example Word addr Binary addr Hit/miss Cache block 26 11 010 Miss 010 Index V 000

N 001 N 010 Y 011 N 100 N 101 N 110

Y 111 N Tag Data 11 Mem[11010] 10 Mem[10110] Cache Example Word addr Binary addr

Hit/miss Cache block 22 10 110 Hit 110 26 11 010 Hit 010 Index

V 000 N 001 N 010 Y 011 N 100 N 101

N 110 Y 111 N Tag Data 11 Mem[11010] 10 Mem[10110]

Cache Example Word addr Binary addr Hit/miss Cache block 16 10 000 Miss 000 3 00 011 Miss

011 16 10 000 Hit 000 Index V Tag Data 000 Y 10

Mem[10000] 001 N 010 Y 11 Mem[11010] 011 Y 00 Mem[00011]

100 N 101 N 110 Y 10 Mem[10110] 111 N Cache Example Word addr

Binary addr Hit/miss Cache block 18 10 010 Miss 010 Index V Tag Data 000

Y 10 Mem[10000] 001 N 010 Y 10 Mem[10010] 011 Y

00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N

Address Subdivision Example: Larger Block Size 64 blocks, 16 bytes/block To what block number does address 1200 map? Block address = 1200/16 = 75 Block number = 75 modulo 64 = 11 31 10 9 4 3 0 Tag Index Offset

22 bits 6 bits 4 bits Block Size Considerations Larger blocks should reduce miss rate Due to spatial locality But in a fixed-sized cache Larger blocks fewer of them More competition increased miss rate Larger blocks pollution Larger miss penalty Can override benefit of reduced miss rate Early restart and critical-word-first can help Cache Misses On cache hit, CPU proceeds normally

On cache miss Stall the CPU pipeline Fetch block from next level of hierarchy Instruction cache miss Restart instruction fetch Data cache miss Complete data access Write-Through On data-write hit, could just update the block in cache But then cache and memory would be inconsistent Write through: also update memory But makes writes take longer e.g., if base CPI = 1, 10% of instructions are stores, write to memory takes 100 cycles Effective CPI = 1 + 0.1100 = 11 Solution: write buffer Holds data waiting to be written to memory CPU continues immediately

Only stalls on write if write buffer is already full Write-Back Alternative: On data-write hit, just update the block in cache Keep track of whether each block is dirty When a dirty block is replaced Write it back to memory Can use a write buffer to allow replacing block to be read first Write Allocation What should happen on a write miss? Alternatives for write-through Allocate on miss: fetch the block Write around: dont fetch the block Since programs often write a whole block before reading it (e.g., initialization) For write-back Usually fetch the block Measuring Cache Performance

Components of CPU time Program execution cycles Includes cache hit time Memory stall cycles Mainly from cache misses With simplifying assumptions: Memory stall cycles Memory accesses Miss rate Miss penalty Program Instructio ns Misses Miss penalty Program Instructio n

Cache Performance Example Given I-cache miss rate = 2% D-cache miss rate = 4% Miss penalty = 100 cycles Base CPI (ideal cache) = 2 Load & stores are 36% of instructions Miss cycles per instruction I-cache: 0.02 100 = 2 D-cache: 0.36 0.04 100 = 1.44 Actual CPI = 2 + 2 + 1.44 = 5.44 Ideal CPU is 5.44/2 =2.72 times faster

Average Access Time Hit time is also important for performance Average memory access time (AMAT) AMAT = Hit time + Miss rate Miss penalty Example CPU with 1ns clock, hit time = 1 cycle, miss penalty = 20 cycles, I-cache miss rate = 5% AMAT = 1 + 0.05 20 = 2ns 2 cycles per instruction Associative Caches Fully associative Allow a given block to go in any cache entry Requires all entries to be searched at once Comparator per entry (expensive) n-way set associative Each set contains n entries Block number determines which set (Block number) modulo (#Sets in cache)

Search all entries in a given set at once n comparators (less expensive) Associative Cache Example Spectrum of Associativity For a cache with 8 entries Associativity Example Compare 4-block caches Direct mapped, 2-way set associative, fully associative Block access sequence: 0, 8, 0, 6, 8 Direct mapped Block address Cache index Hit/miss

0 8 0 6 8 0 0 0 2 0 miss miss miss miss miss 0 Mem[0] Mem[8] Mem[0]

Mem[0] Mem[8] Cache content after access 1 2 Mem[6] Mem[6] 3 Associativity Example 2-way set associative Block address Cache index

Hit/miss 0 8 0 6 8 0 0 0 0 0 miss miss hit miss miss Cache content after access Set 0 Set 1

Mem[0] Mem[0] Mem[0] Mem[0] Mem[8] Mem[8] Mem[8] Mem[6] Mem[6] Fully associative Block address 0 8 0 6 8 Hit/miss miss miss

hit miss hit Cache content after access Mem[0] Mem[0] Mem[0] Mem[0] Mem[0] Mem[8] Mem[8] Mem[8] Mem[8] Mem[6] Mem[6] How Much Associativity Increased associativity decreases miss rate But with diminishing returns

Simulation of a system with 64KB D-cache, 16-word blocks, SPEC2000 1-way: 2-way: 4-way: 8-way: 10.3% 8.6% 8.3% 8.1% Set Associative Cache Organization Replacement Policy Direct mapped: no choice Set associative

Prefer non-valid entry, if there is one Otherwise, choose among entries in the set Least-recently used (LRU) Choose the one unused for the longest time Simple for 2-way, manageable for 4-way, too hard beyond that Random Gives approximately the same performance as LRU for high associativity Write Policy Write-through Update both upper and lower levels Simplifies replacement, but may require write buffer Write-back Update upper level only

Update lower level when block is replaced Need to keep more state Virtual memory Only write-back is feasible, given disk write latency Sources of Misses Compulsory misses (aka cold start misses) First access to a block Capacity misses Due to finite cache size A replaced block is later accessed again Conflict misses (aka collision misses) In a non-fully associative cache Due to competition for entries in a set Would not occur in a fully associative cache of the same total size Cache Design Trade-offs Design change

Effect on miss rate Negative performance effect Increase cache size Decrease capacity misses May increase access time Increase associativity Decrease conflict misses May increase access time Increase block size

Decrease compulsory Increases miss misses penalty. For very large block size, may increase miss rate due to pollution. Cache Control Example cache characteristics Direct-mapped, write-back, write allocate Block size: 4 words (16 bytes) Cache size: 16 KB (1024 blocks) 32-bit byte addresses Valid bit and dirty bit per block Blocking cache

CPU waits until access is complete 31 10 9 4 3 0 Tag Index Offset 18 bits 10 bits 4 bits Block Placement

Determined by associativity Direct mapped (1-way associative) One choice for placement n-way set associative n choices within a set Fully associative Any location Higher associativity reduces miss rate Increases complexity, cost, and access time Finding a Block Associativity Direct mapped n-way set associative Fully associative Location method Index Set index, then search

entries within the set Search all entries Full lookup table Tag comparisons 1 n #entries 0 Hardware caches Reduce comparisons to reduce cost Virtual memory Full table lookup makes full associativity feasible Benefit in reduced miss rate Replacement Choice of entry to replace on a miss Least recently used (LRU) Complex and costly hardware for high associativity Random

Close to LRU, easier to implement Virtual memory LRU approximation with hardware support Virtual Memory Use main memory as a cache for secondary (disk) storage Managed jointly by CPU hardware and the operating system (OS) Programs share main memory Each gets a private virtual address space holding its frequently used code and data Protected from other programs CPU and OS translate virtual addresses to physical addresses VM block is called a page VM translation miss is called a page fault

Address Translation Fixed-size pages (e.g., 4K) Page Fault Penalty On page fault, the page must be fetched from disk Takes millions of clock cycles Handled by OS code Try to minimize page fault rate Fully associative placement Smart replacement algorithms Page Tables Stores placement information Array of page table entries, indexed by virtual page number Page table register in CPU points to page table in physical memory If page is present in memory PTE stores the physical page number Plus other status bits (referenced, dirty, ) If page is not present

PTE can refer to location in swap space on disk Translation Using a Page Table Mapping Pages to Storage Replacement and Writes To reduce page fault rate, prefer least-recently used (LRU) replacement Reference bit (aka use bit) in PTE set to 1 on access to page Periodically cleared to 0 by OS A page with reference bit = 0 has not been used recently Disk writes take millions of cycles Block at once, not individual locations Write through is impractical Use write-back Dirty bit in PTE set when page is written

Fast Translation Using a TLB Address translation would appear to require extra memory references One to access the PTE Then the actual memory access But access to page tables has good locality So use a fast cache of PTEs within the CPU Called a Translation Look-aside Buffer (TLB) Typical: 16512 PTEs, 0.51 cycle for hit, 10100 cycles for miss, 0.01%1% miss rate Misses could be handled by hardware or software Fast Translation Using a TLB TLB Misses If page is in memory Load the PTE from memory and retry Could be handled in hardware Can get complex for more complicated page table structures Or in software

Raise a special exception, with optimized handler If page is not in memory (page fault) OS handles fetching the page and updating the page table Then restart the faulting instruction TLB Miss Handler TLB miss indicates Page present, but PTE not in TLB Page not preset Must recognize TLB miss before destination register overwritten Raise exception Handler copies PTE from memory to TLB Then restarts instruction If page not present, page fault will occur Page Fault Handler Use faulting virtual address to find PTE Locate page on disk Choose page to replace

If dirty, write to disk first Read page into memory and update page table Make process runnable again Restart from faulting instruction TLB and Cache Interaction If cache tag uses physical address Need to translate before cache lookup Alternative: use virtual address tag Complications due to aliasing Different virtual addresses for shared physical address Chapter 5 Large and Fast: Exploiting Memory Hierarchy 66

Concluding Remarks Fast memories are small, large memories are slow We really want fast, large memories Caching gives this illusion Principle of locality Programs use a small part of their memory space frequently Memory hierarchy L1 cache L2 cache DRAM memory disk Memory system design is critical for multiprocessors

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