Digital Systems: Hardware Organization and Design

Digital Systems: Hardware Organization and Design

Microcomputer Systems 2 Universal Asynchronous Receiver Transmitter (UART) LAB 1 Distributive Computing RST232 February 26, 2020 Veton Kpuska 2 BF533 UART Port Controller Reference: ADSP-BF533 Blackfin Processor Hardware Reference (doc: BF533_hwr.pdf) February 26, 2020

Veton Kpuska 3 BF533 UART Port Controller The Universal Asynchronous Receiver/Transmitter (UART) is a The serial communication follows an asynchronous protocol that supports various full-duplex peripheral compatible with PC-style industry-standard

UARTs. The UART converts data between serial and parallel formats. word length, stop bits, and parity generation options. The UART includes interrupt handling hardware. Interrupts can be generated from 12 different events. February 26, 2020 Veton Kpuska 4 BF533 UART Port Controller The UART is a DMA-capable peripheral with support for separate TX and RX DMA master channels.

It can be used in either DMA or programmed non-DMA mode of operation. The non-DMA mode requires software management of the data flow using either interrupts or polling. The DMA method requires minimal software intervention as the DMA engine itself moves the data. See Chapter 9 of HRM, Direct Memory Access for more information on DMA. Either one of the peripheral timers can be used to provide a hardware assisted auto-baud detection mechanism for use with the UART. See Chapter 15 of HRM, Timers, for more information.

February 26, 2020 Veton Kpuska 5 Serial Communication The UART follows an asynchronous serial communication protocol with these options: 5 8 data bits 1, 1, or 2 stop bits None, even, or odd parity Baud rate = SCLK/(16 Divisor), where SCLK is the system clock

frequency and Divisor can be a value from 1 to 65536 All data words require a start bit and at least one stop bit. With the optional parity bit, this creates a 7- to 12-bit range for each word. The format of received and transmitted character frames is controlled by the Line Control register (UART_LCR). Data is always transmitted and received least significant bit (LSB) first. February 26, 2020 Veton Kpuska 6 Bitstream on the TX Pin

Stop Bit Data Bits B0 B1 B2 B3 B4 B5 B6 Start LSB Bit

February 26, 2020 B7 Parity Bit Optional ODD or EVEN Veton Kpuska 7 UART Control and Status Registers The processor provides a set of PC-style industry-standard control and status registers for each UART.

Control and Status Registers are Memory Mapped Registers (MMR). These Memory-Mapped Registers (MMRs) are byte-wide registers that are mapped as half words with the most significant byte zero filled. Line Control Register (UART_LCR) The Modem Control register (UART_MCR) The UART Line Status register (UART_LSR) Divisor Latch Registers: (UART_DLH and UART_DLL) Transmit Holding Register: (UART_THR) Receive Buffer Register: (UART_RBR) Interrupt Enable Register: (UART_IER). Consistent with industry-standard interfaces, multiple registers are mapped

to the same address location. Transmit and receive channels are both buffered. The UART_THR register buffers the Transmit Shift register (TSR) and The UART_RBR register buffers the Receive Shift register (LSR). The shift registers are not directly accessible by software. February 26, 2020 Veton Kpuska 8 UART Control and Status Registers: UART Line Control Register

UART_LCR Register The UART Line Control register (UART_LCR) controls the format of received and transmitted character frames. The SB bit functions even when the UART clock is disabled. Since the TX pin normally drives high, it can be used as a flag output pin,

if the UART is not used. February 26, 2020 Veton Kpuska 9 UART Control and Status Registers: Modem Control Register UART_MCR Register The Modem Control register (UART_MCR)

controls the UART port, as shown in Figure 13-3. Even if modem functionality is not supported, the Modem Control register is available in order to support Loopback mode forces the TX pin to high the loopback and disconnects the receivers input from mode. the RX pin, but redirects it to the transmit output internally. February 26, 2020 Veton Kpuska 10

UART Control and Status Registers: UART Line Status Register UART_LSR Register The UART Line Status register (UART_LSR) contains UART status information as shown in Figure 13-4. February 26, 2020 Veton Kpuska

11 UART Line Status Register The following bits are cleared when the UART Line Status Register (UART_LSR) is read: The Break Interrupt (BI), Overrun Error (OE), Parity Error (PE) and Framing Error (FE). The Data Ready (DR) bit is cleared when the UART Receive Buffer Register (UART_RBR) is read.

Important Note: Because of the destructive nature of these read operations, special care should be taken. For more information, see Speculative Load Execution on page 6-69 and Conditional Load Behavior on page 6-70. February 26, 2020 Veton Kpuska 12 UART Line Status Register The THRE bit indicates that the UART transmit channel is ready for new data and software can write to UART_THR.

Writes to UART_THR clear the THRE bit. It is set again when data is copied from UART_THR to the Transmit Shift register (TSR). The TEMT bit can be evaluated to determine whether a recently initiated transmit operation has been completed. February 26, 2020 Veton Kpuska 13 UART Control and Status Registers: UART_THR Register A write to the

UART Transmit Holding register (UART_THR) initiates the transmit operation. The data is moved to the internal Transmit Shift register (TSR) where it is shifted out at a baud rate equal to SCLK/(16 Divisor) with start, stop, and parity bits appended as required. February 26, 2020

Veton Kpuska 14 UART_THR Register All data words begin with a 1-to-0-transition start bit. The transfer of data from UART_THR to the Transmit Shift register (TSR) sets the Transmit Holding Register Empty (THRE) status flag in the UART Line Status register (UART_LSR). The write-only UART_THR register is mapped to the same address as the read-only UART_RBR and UART_DLL registers.

To access UART_THR, the DLAB bit in UART_LCR must be cleared. When the DLAB bit is cleared, writes to this address target the UART_THR register, and reads from this address return the UART_RBR register. Note data is transmitted and received least significant bit (LSB) first (bit 0) followed by the most significant bits (MSBs). February 26, 2020 Veton Kpuska 15

UART Control and Status Registers: UART_RBR Register UART_RBR Register The receive operation uses the same data format as the transmit configuration, except that the number of stop bits is always assumed to be 1. After detection of the start bit, the received word is shifted into the Receive Shift

register (RSR) at a baud rate of SCLK/(16 x Divisor). After the appropriate number of bits (including stop bit) is received, the data and any status are updated and the Receive Shift register is transferred to the UART Receive Buffer register (UART_RBR), shown in Figure 13-6. After the transfer of the received word to the UART_RBR buffer and the appropriate synchronization delay, the Data Ready (DR) status flag is updated. February 26, 2020 Veton Kpuska

16 UART_RBR Register Sampling Clock Issues: A sampling clock equal to 16 times the baud rate samples the data as close to the midpoint of the bit as possible. Because the internal sample clock may not exactly match the asynchronous receive data rate, the sampling point drifts from the center of each bit. The sampling point is synchronized again with each start bit, so the error accumulates only over the length of a single word.

A receive filter removes spurious pulses of less than two times the sampling clock period. The read-only UART_RBR register is mapped to the same address as the write-only UART_THR and UART_DLL registers. To access UART_RBR, the DLAB bit in UART_LCR must be cleared. When the DLAB bit is cleared, writes to this address target the UART_THR register, while reads from this address return the UART_RBR register. February 26, 2020 Veton Kpuska 17

UART Control and Status Registers: UART_IER Register UART_IER Register The UART Interrupt Enable register (UART_IER) is used to enable requests for system handling of empty or full states of UART data registers. Unless polling is used as a means of action, the ERBFI and/or ETBEI bits in this register are normally set. February 26, 2020

Veton Kpuska 18 UART_IER Register Non DMA data transfers Setting this register without enabling system DMA causes the UART to notify the processor of data inventory state by means of interrupts. For proper operation in this mode, system interrupts must be enabled, and appropriate interrupt handling routines must be present. For backward compatibility, the UART_IIR still reflects the correct interrupt status. Important Note: The UART features three separate

interrupt channels to handle data transmit, data receive, and line status events independently, regardless whether DMA is enabled or not. February 26, 2020 Veton Kpuska 19 UART_IER Register DMA data transfers With system DMA enabled, the UART uses DMA to transfer data to or from the processor.

Dedicated DMA channels are available to receive and transmit operation. Line error handling can be configured completely independently from the receive/transmit setup. The UART_IER register is mapped to the same address as UART_DLH. To access UART_IER, the DLAB bit in UART_LCR must be cleared. February 26, 2020 Veton Kpuska 20 UART_IER Register: DMA UARTs DMA is enabled by first setting up the system DMA control registers, and

then enabling the UART ERBFI and/or ETBEI interrupts in the UART_IER register. This is because the interrupt request lines double as DMA request lines. Depending on whether DMA is enabled or not, upon receiving these requests, the DMA control unit either generates a direct memory access or passes the UART interrupt on to the system interrupt handling unit. However, UARTs error interrupt goes directly to the system interrupt handling unit, bypassing the DMA unit completely. February 26, 2020

Veton Kpuska 21 UART_IER Register: DMA The ELSI bit enables interrupt generation on an independent interrupt channel when any of the following conditions are raised by the respective bit in the UART Line Status register (UART_LSR): Receive Overrun Error (OE) Receive Parity Error (PE) Receive Framing Error (FE) Break Interrupt (BI) When the ETBEI bit is set in the UART_IER register, the UART module

immediately issues an interrupt or DMA request. When initiating the transmission of a string, no special handling of the first character is required. Set the ETBEI bit and let the interrupt service routine load the first character from memory and write it to the UART_THR register in the normal manner. Accordingly, the ETBEI bit should be cleared if the string transmission has completed. February 26, 2020 Veton Kpuska

22 UART Control and Status Registers: UART_IIR Register UART_IIR Register For legacy reasons, the UART Interrupt Identification register (UART_IIR) still reflects the UART interrupt status. Legacy operation may require bundling all UART interrupt sources to a single interrupt channel and servicing them all by the same software routine. This can be established by globally assigning all UART interrupts to the same interrupt priority, by using the System Interrupt Controller (SIC). When cleared, the Pending Interrupt bit (NINT) signals that an

interrupt is pending. The STATUS field indicates the highest priority pending interrupt. The receive line status has the highest priority; the UART_THR empty interrupt has the lowest priority. In the case where both interrupts are signaling, the UART_IIR reads 0x06. February 26, 2020 Veton Kpuska 23 UART Control and Status Registers: UART_IIR Register When a UART interrupt is pending, the interrupt

service routine (ISR) needs to clear the interrupt latch explicitly. The following figure (next slide) shows how to clear any of the three latches. The TX interrupt request is cleared by writing new data to the UART_THR register or by reading the UART_IIR register. Please note the special role of the UART_IIR register read in the case where the service routine does not want to transmit further data. February 26, 2020 Veton Kpuska

24 UART Control and Status Registers: UART_IIR Register UART_IIR Register February 26, 2020 Veton Kpuska 25 UART Control and Status Registers: UART_IIR Register If software stops transmission, it must read the UART_IIR register to reset the interrupt request.

As long as the UART_IIR register reads 0x04 or 0x06 (indicating that another interrupt of higher priority is pending), the UART_THR empty latch cannot be cleared by reading UART_IIR. Important Note: If either the Line Status interrupt or the Receive Data interrupt has been assigned a lower interrupt priority by the SIC, a deadlock condition can occur. To avoid this, always assign the lowest priority of the enabled UART interrupts to the UART_THR empty event. Because of the destructive nature of these read operations, special care should be taken. For more information, see Speculative Load Execution on page 6-69 and Conditional Load Behavior on page 6-70.

February 26, 2020 Veton Kpuska 26 UART Control and Status Registers: UART_DLL and UART_DLH Registers UART_DLL and UART_DLH Registers The bit rate is characterized by the system clock (SCLK) and the 16-bit Divisor. The Divisor is split into the UART Divisor Latch

Low Byte register (UART_DLL) and The UART Divisor Latch High Byte register (UART_DLH). Both registers together form a 16-bit Divisor. The baud clock is divided by 16 so that: BAUD RATE = SCLK/(16 x Divisor) Divisor = 65,536 when UART_DLL = UART_DLH = 0 February 26, 2020 Veton Kpuska 27 UART_DLL and UART_DLH Registers

The UART_DLL register is mapped to the same address as the UART_THR and UART_RBR registers. The UART_DLH register is mapped to the same address as the Interrupt Enable register (UART_IER). The DLAB bit in UART_LCR must be set before the UART Divisor Latch registers can be accessed. Important Note:

The 16-bit Divisor formed by UART_DLH and UART_DLL resets to 0x0001, resulting in the highest possible clock frequency by default. If the UART is not used, disabling the UART clock will save power. The UART_DLH and UART_DLL registers can be programmed by software before or after setting the UCEN bit. February 26, 2020 Veton Kpuska 28 UART_DLL and UART_DLH Registers

February 26, 2020 Veton Kpuska 29 UART Control and Status Registers: UART_SCR Register UART_SCR Register It is used for generalpurpose data storage and does not control the UART hardware in any way. The contents of the 8bit UART Scratch register (UART_SCR) is reset to 0x00.

February 26, 2020 Veton Kpuska 30 UART Control and Status Registers: UART_GCTL Register UART_GCTL Register The UART Global Control register (UART_GCTL) contains the enable bit for internal UART clocks and for the IrDA mode of operation of the

UART. February 26, 2020 Veton Kpuska 31 UART_GCTL Register Infrared Data Association (IrDA) Serial Infrared Physical Layer Link Specification (SIR) protocol. The IrDA TX Polarity Change bit and the IrDA RX Polarity Change bit are effective only in IrDA mode. The two force error bits, FPE and FFE,

are intended for test purposes. They are useful for debugging software, especially in loopback mode. February 26, 2020 Veton Kpuska 32 DMA Mode of UART In this mode, separate receive (RX) and transmit (TX) DMA channels move data between the UART and memory. The software does not have to move data, it just has to set up the appropriate transfers either through

the descriptor mechanism or through Autobuffer mode. No additional buffering is provided in the UART DMA channel, so the latency requirements are the same as in non-DMA mode. However, the latency is determined by the bus activity and arbitration mechanism and not by the processor loading and interrupt priorities. For more information, see Chapter 9, Direct Memory Access. February 26, 2020 Veton Kpuska 33 DMA Mode of UART

DMA interrupt routines must explicitly write 1s to the corresponding DMA IRQ status registers to clear the latched request of the pending interrupt. The UARTs DMA is enabled by first setting up the system DMA control registers and then enabling the UART ERBFI and/or ETBEI interrupts in the UART_IER register. Depending on whether DMA is enabled or not, upon receiving these requests, the DMA control unit either

This is because the interrupt request lines double as DMA request lines. generates a direct memory access or passes the UART interrupt on to the system interrupt handling unit. However, the UARTs error interrupt goes directly to the system interrupt handling unit, bypassing the DMA unit completely. The UARTs DMA supports 8-bit operation. February 26, 2020 Veton Kpuska 34 BF533 Direct Memory Access - DMA BF533 DMA Support Processor Memory Architecture

February 26, 2020 Veton Kpuska 36 BF533 DMA Support The processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the core. DMA transfers can occur between the internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM

controller and the asynchronous memory controller. DMAcapable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. February 26, 2020 Veton Kpuska 37

BF533 DMA Support The DMA controller supports both one-dimensional (1D) and two-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to +/32K elements. Furthermore, the column step size can be less than the row step size, allowing

implementation of interleaved datastreams. This feature is especially useful in video applications where data can be de-interleaved on the fly. February 26, 2020 Veton Kpuska 38 Generic Names of the DMA Memory-Mapped Registers February 26, 2020 Veton Kpuska 39 DMA Channel Map February 26, 2020

Veton Kpuska 40 DMA Channel Map February 26, 2020 Veton Kpuska 41 Analysis of Basic UART Implementation Communication of BF533 EZ-Kit Lite via RS-232 UART UART RS-232 February 26, 2020

Veton Kpuska 43 UART Transmit Configuration UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA7_CONFIG = 0x0; // Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081;

February 26, 2020 Veton Kpuska See Slide: DMA Ch annel M ap 45 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000;

//Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 46 UART Line Control Register *pUART_LCR *pUART_LCR == 0x0080 0x0080 == 0000 0000 0000 0000 1000 1000 0000 0000;;

February 26, 2020 Veton Kpuska 47 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; }

February 26, 2020 Veton Kpuska 48 UART Divisort Latch Registers *pUART_DLL *pUART_DLL == 0x0000 0x0000 == 0000 0000 0000 0000 0000 0000 0000 0000;; *pUART_DLh *pUART_DLh == 0x00FF 0x00FF == 0000 0000 0000 0000 1111 1111 1111; 1111;

February 26, 2020 Veton Kpuska 49 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; }

February 26, 2020 Veton Kpuska See Slide: UART_IER Register 50 UART Line Control Register *pUART_LCR *pUART_LCR == 0x0000 0x0000 == 0000 0000 0000 0000 0000 0000 0000 0000;; *pUART_LCR *pUART_LCR == 0x0007 0x0007 == 0000 0000 0000

0000 0000 0000 0111; 0111; February 26, 2020 Veton Kpuska 51 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit

*pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 52 UART Interrupt Enable Register *pUART_IER *pUART_IER == 0x0002 0x0002 == 0000 0000 0000 0000 0000 0000 0010; 0010; February 26, 2020 Veton Kpuska

53 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska

54 UART_GCTL Register *pUART_GCLT *pUART_GCLT == 0x0001 0x0001 == 0000 0000 0000 0000 0000 0000 0001; 0001; February 26, 2020 Veton Kpuska 55 DMA Configuration DMA Channels Peripheral Map Register

Each DMA channels Peripheral Map register (DMAx_PERIPHERAL_MAP) contains bits that: Map the channel to a specific peripheral. Identify whether the channel is a Peripheral DMA channel or a Memory DMA channel. *pDMA7_PERIPHERAL_MAP *pDMA7_PERIPHERAL_MAP==0x7000; 0x7000; February 26, 2020 Veton Kpuska 57 UART Configuration in DMA Mode /********************************************************

Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA7_CONFIG = 0x0; // Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081; February 26, 2020 Veton Kpuska 58 DMA Configuration Register

The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. *pDMA7_CONFIG *pDMA7_CONFIG == 0x0 0x0;; February 26, 2020 Veton Kpuska 59 UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART()

{ // Clear the DMA configuration register *pDMA7_CONFIG = 0x0; // Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081; February 26, 2020 Veton Kpuska 60 DMA Configuration Register The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure

9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. *pDMA7_CONFIG *pDMA7_CONFIG == 0x1081 0x1081 == 0001 0001 0000 0000 1000 1000 0001 0001;; February 26, 2020 Veton Kpuska 61 Transmit_uart_533.c /******************************************************* This example code tests the UART using the stop mode DMA across two kits. This code is the transmitter code. *******************************************************/

#include #include #include #include #define BUFFER_SIZE 16 /******************************************************* Function declarations *******************************************************/ void setup_UART(); void setup_interrupts(); /******************************************************* ISR declarations *******************************************************/ EX_INTERRUPT_HANDLER(transmit_isr); /******************************************************* Variable declarations

*******************************************************/ char tx_buffer[BUFFER_SIZE]; volatile unsigned int tx_cnt = 0; February 26, 2020 Veton Kpuska 62 DMA Start Address Register The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA. February 26, 2020 Veton Kpuska

63 UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA7_CONFIG = 0x0; // Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081; February 26, 2020

Veton Kpuska 64 DMA Count Register For 1D DMA, it specifies the number of elements to read in. For 2D DMA details, see Two-Dimensional DMA on page 9-45 of ADSP-BF533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements. February 26, 2020 Veton Kpuska 65 UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/

void setup_UART() { // Clear the DMA configuration register *pDMA7_CONFIG = 0x0; // Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081; February 26, 2020 Veton Kpuska 66 DMAx Modify Register

The Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, twoscomplement byte-address increment. In 1D DMA, this increment is the stride that is applied after transferring each element. Note X_MODIFY is specified in bytes, regardless of the DMA transfer size. February 26, 2020 Veton Kpuska 67 UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA7_CONFIG = 0x0;

// Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081; February 26, 2020 Veton Kpuska 68 DMA Configuration Register The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes.

*pDMA7_CONFIG = 0x1081 February 26, 2020 Veton Kpuska 69 UART Port Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; // 5 bit data *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit

*pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 70 UART Line Control Register *pUART_LCR = 0x0080 February 26, 2020 Veton Kpuska 71 UART Control Registers Configuration // Configure the UART Control Registers

// Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 72 UART Divisor Latch Low Byte Register

Divisor = 0x000000FF = 255 *pUART_DLL = 0x00FF *pUART_DLH = 0x0000 February 26, 2020 Veton Kpuska 73 Boud-Rate BAUD RATE = SCLK/(16 x Divisor) SCLK/(16x255) = SCLK/4096 SCLK = 100 MHz

BAUD RATE = 100 MHz /4096 = 24414.0625 bps SCLK = 54 MHz BAUD RATE = 54 MHz /4096 = 13183.59375 bps February 26, 2020 Veton Kpuska 74 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access

*pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 75 UART Line Control Register Resetting UART_LRC Register

*pUART_LRC = 0x0000 February 26, 2020 Veton Kpuska 76 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x01FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled

*pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 77 UART Line Control Register Setting UART_LRC Register *pUART_LRC = 0x0007 February 26, 2020 Veton Kpuska 78 UART Control Registers Configuration

// Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x01FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 79 UART_IER Interrupt Enable Register

*pUART_IER = 0x0002 February 26, 2020 Veton Kpuska 80 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x01FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity with 2 Stop Bits *pUART_LCR = 0x0007; //Enable interrupts for transmit *pUART_IER = 0x0002; // UART Clock Enabled

*pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 81 UART_GCTL UART Global Control Register *pUART_GCTL = 0x0001 February 26, 2020 Veton Kpuska 82 UART Receive Configuration UART Configuration in DMA Mode /********************************************************

Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA6_CONFIG = 0x0; // Configure the UART DMA parameter registers // Receive DMA *pDMA6_START_ADDR = rx_buffer; *pDMA6_X_COUNT = BUFFER_SIZE; *pDMA6_X_MODIFY = 1; *pDMA6_CONFIG = 0x0083; February 26, 2020 Veton Kpuska 84 UART Control Registers Configuration // Configure the UART Control Registers

// Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity *pUART_LCR = 0x0003; // Note the Manufacturers // Hardware Bug //Enable interrupts for receive *pUART_IER = 0x0001; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 85 DMA Configuration

DMA Channels Peripheral Map Register Each DMA channels Peripheral Map register (DMAx_PERIPHERAL_MAP) contains bits that: Map the channel to a specific peripheral. Identify whether the channel is a Peripheral DMA channel or a Memory DMA channel. *pDMA6_PERIPHERAL_MAP *pDMA6_PERIPHERAL_MAP==0x6000; 0x6000; See Slide: DMA Ch annel M ap

February 26, 2020 Veton Kpuska 87 UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA6_CONFIG = 0x0; // Configure the UART DMA parameter registers // Receive DMA *pDMA6_START_ADDR = rx_buffer; *pDMA6_X_COUNT = BUFFER_SIZE; *pDMA6_X_MODIFY = 1; *pDMA6_CONFIG = 0x0083;

February 26, 2020 Veton Kpuska 88 DMA Configuration Register The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. February 26, 2020 Veton Kpuska 89 UART Configuration in DMA Mode /********************************************************

Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA6_CONFIG = 0x0; // Configure the UART DMA parameter registers // Receive DMA *pDMA6_START_ADDR = rx_buffer; *pDMA6_X_COUNT = BUFFER_SIZE; *pDMA6_X_MODIFY = 1; *pDMA6_CONFIG = 0x0083; February 26, 2020 Veton Kpuska 90 Receive_uart_533.c /******************************************************* This example code tests the UART using the stop mode DMA

across two kits. This code is the receiver code. *******************************************************/ #include #include #include #include #define BUFFER_SIZE 10000 /******************************************************* Function declarations *******************************************************/ void setup_UART(); void setup_interrupts(); /******************************************************* ISR declarations *******************************************************/ EX_INTERRUPT_HANDLER(receive_isr); /*********************** ******************************** Variable declarations *******************************************************/ char rx_buffer[BUFFER_SIZE]; volatile unsigned int rx_cnt = 0;

February 26, 2020 Veton Kpuska 91 DMA Start Address Register The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA. February 26, 2020 Veton Kpuska 92 UART Configuration in DMA Mode

/******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA6_CONFIG = 0x0; // Configure the UART DMA parameter registers // Receive DMA *pDMA6_START_ADDR = rx_buffer; *pDMA6_X_COUNT = BUFFER_SIZE; *pDMA6_X_MODIFY = 1; *pDMA6_CONFIG = 0x0083; February 26, 2020 Veton Kpuska 93 DMA Count Register

For 1D DMA, it specifies the number of elements to read in. For 2D DMA details, see Two-Dimensional DMA on page 9-45 of ADSP-BF533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements. February 26, 2020 Veton Kpuska 94 UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA6_CONFIG = 0x0; // Configure the UART DMA parameter registers // Receive DMA

*pDMA6_START_ADDR = rx_buffer; *pDMA6_X_COUNT = BUFFER_SIZE; *pDMA6_X_MODIFY = 1; *pDMA6_CONFIG = 0x0083; February 26, 2020 Veton Kpuska 95 DMAx Modify Register The Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, twoscomplement byte-address increment. In 1D DMA, this increment is the stride that is applied after transferring each element. Note X_MODIFY is specified in bytes, regardless of the DMA transfer size.

February 26, 2020 Veton Kpuska 96 UART Configuration in DMA Mode /******************************************************** Function to configure the UART & DMA ********************************************************/ void setup_UART() { // Clear the DMA configuration register *pDMA6_CONFIG = 0x0; // Configure the UART DMA parameter registers // Receive DMA *pDMA6_START_ADDR = rx_buffer; *pDMA6_X_COUNT = BUFFER_SIZE; *pDMA6_X_MODIFY = 1; *pDMA6_CONFIG = 0x0083; February 26, 2020

Veton Kpuska 97 DMA Configuration Register The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. *pDMA6_CONFIG = 0x0083 February 26, 2020 Veton Kpuska 98 UART Control Registers

Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity *pUART_LCR = 0x0003; //Enable interrupts for receive *pUART_IER = 0x0001; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 99 UART Line Control Register

*pUART_LCR = 0x0080 February 26, 2020 Veton Kpuska 100 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x01FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity *pUART_LCR = 0x0003; //Enable interrupts for receive *pUART_IER = 0x0001; // UART Clock Enabled

*pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 101 UART Divisor Latch Low Byte Register Divisor = 0x000001FF = 255 *pUART_DLL = 0x00FF *pUART_DLH = 0x0000 February 26, 2020 Veton Kpuska 102

Boud-Rate BAUD RATE = SCLK/(16 x Divisor) SCLK/(16x255) = SCLK/4096 SCLK = 100 MHz BAUD RATE = 100 MHz /4096 = 24414.0625 bps SCLK = 54 MHz BAUD RATE = 54 MHz /4096 = 13183.59375 bps

February 26, 2020 Veton Kpuska 103 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity *pUART_LCR = 0x0003; //Enable interrupts for receive *pUART_IER = 0x0001; // UART Clock Enabled *pUART_GCTL = UCEN;

} February 26, 2020 Veton Kpuska 104 UART Line Control Register *pUART_LCR = 0x0000 February 26, 2020 Veton Kpuska 105 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000;

*pUART_DLL = 0x00FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity *pUART_LCR = 0x0003; // Work-around for hardware bug-anomaly // http://www.analog.com/UploadedFiles/REDESIGN_IC_Anomalies/170183728ADSP.BF533.Blackfin. Anomaly.List.for.Revisions.0.3.0.4.0.5.Rev.W.12.07.06.pdf //Enable interrupts for receive *pUART_IER = 0x0001; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 106 UART Line Control Register

Setting UART_LRC Register *pUART_LRC = 0x0003 February 26, 2020 Veton Kpuska 107 UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x01FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity *pUART_LCR = 0x0003;

//Enable interrupts for receive *pUART_IER = 0x0001; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 108 UART_IER Interrupt Enable Register *pUART_IER = 0x0001 February 26, 2020 Veton Kpuska 109 UART Control Registers

Configuration // Configure the UART Control Registers // Enable the divisor latch access *pUART_LCR = 0x0080; *pUART_DLH = 0x0000; *pUART_DLL = 0x01FF; // disable the divisor latch access *pUART_LCR = 0x0000; //Enable 8-bit mode without parity *pUART_LCR = 0x0003; //Enable interrupts for receive *pUART_IER = 0x0001; // UART Clock Enabled *pUART_GCTL = UCEN; } February 26, 2020 Veton Kpuska 110 UART_GCTL

UART Global Control Register *pUART_GCTL = 0x0001 February 26, 2020 Veton Kpuska 111 Event Handling UART Transmit Event Handling Functions /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priorities for UART transmit *pSIC_IAR1 = 0x3FFFFFFF //Assign ISR to this interrupt register_handler(ik_ivg10, transmit_isr);

//Unmask the UART transmit interrupt *pSIC_IMASK = 0x00008000; } /******************************************************** UART transmit interrupt service routine ********************************************************/ EX_INTERRUPT_HANDLER(transmit_isr) { *pDMA7_IRQ_STATUS |= DMA_DONE; //clear the interrupt tx_cnt++; } February 26, 2020 Veton Kpuska 113 System Event Mapping February 26, 2020

Veton Kpuska 114 Initialization of Interrupts If the default assignments are acceptable, then interrupt initialization involves only: 1. 2. 3. Initialization of the core Event Vector Table (EVT) vector address entries. Why is this needed? Initialization of the IMASK register Unmasking the specific peripheral interrupts in SIC_IMASK that the system requires

February 26, 2020 Veton Kpuska 115 Event Handling Functions /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priorities for UART transmit *pSIC_IAR1 = 0x3FFFFFFF //Assign ISR to this interrupt register_handler(ik_ivg10, transmit_isr); //Unmask the UART transmit interrupt *pSIC_IMASK = 0x00008000; } /******************************************************** UART transmit interrupt service routine ********************************************************/

EX_INTERRUPT_HANDLER(transmit_isr) { *pDMA7_IRQ_STATUS |= DMA_DONE; //clear the interrupt tx_cnt++; } February 26, 2020 Veton Kpuska 116 System Interrupt Assignment Register *pSIC_IAR1 *pSIC_IAR1 == 0x3FFFFFFF 0x3FFFFFFF 0x3fffffff = 0011 0x3fffffff = 0011 1111

1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 DMA7 DMA7(UART (UARTTX) TX) February 26, 2020 Veton Kpuska 117 Event Handling Functions /********************************************************

Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priorities for UART transmit *pSIC_IAR1 = 0x3FFFFFFF See Slide //Assign ISR to this interrupt register_handler(ik_ivg10, transmit_isr); System Event Mapping //Unmask the UART transmit interrupt *pSIC_IMASK = 0x00008000; } /******************************************************** UART transmit interrupt service routine ********************************************************/ EX_INTERRUPT_HANDLER(transmit_isr) { *pDMA7_IRQ_STATUS |= DMA_DONE;

//clear the interrupt tx_cnt++; } February 26, 2020 Veton Kpuska 118 Registering an ISR typedef enum { ik_emulation, ik_reset, ik_nmi, ik_exception, ik_global_int_enable, ik_hardware_err, ik_timer, ik_ivg7, ik_ivg8, ik_ivg9,

ik_ivg10, ik_ivg11, ik_ivg12, ik_ivg13, ik_ivg14, ik_ivg15 } interrupt_kind; ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn, int enable); February 26, 2020 Veton Kpuska 119 Event Handling Functions /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priorities for UART transmit

*pSIC_IAR1 = 0x3FFFFFFF //Assign ISR to this interrupt register_handler(ik_ivg10, transmit_isr); //Unmask the UART transmit interrupt *pSIC_IMASK = 0x00008000; Unmasking Unmaskingof ofthe theInterrupt Interruptby bysetting setting corresponding bits in SIC_IMASK corresponding bits in SIC_IMASKregister. register. } /********************************************************

UART transmit interrupt service routine ********************************************************/ EX_INTERRUPT_HANDLER(transmit_isr) { *pDMA7_IRQ_STATUS |= DMA_DONE; //clear the interrupt tx_cnt++; } February 26, 2020 Veton Kpuska 120 SIC_IMASK Register *pSIC_IMASK *pSIC_IMASK == 0x00008000; 0x00008000; 0x00008000 = 0000

0x00008000 = 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1000 0000 0000 0000 DMA DMAInterrupt Interrupt UART UARTTX TX Do Donot notforget forget to

Unmask to Unmask Interrupt Interrupt associated associated with withPF PF Interrupt InterruptAA February 26, 2020 Veton Kpuska 121 Servicing Interrupts UART TX DMA Interrupt Status Registers

February 26, 2020 Veton Kpuska 123 Servicing Interrupts /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priorities for UART transmit *pSIC_IAR1 = 0x3FFFFFFF //Assign ISR to this interrupt register_handler(ik_ivg10, transmit_isr); //Unmask the UART transmit interrupt *pSIC_IMASK = 0x00008000; } /******************************************************** UART transmit interrupt service routine ********************************************************/

EX_INTERRUPT_HANDLER(transmit_isr) { *pDMA7_IRQ_STATUS |= DMA_DONE; //clear the interrupt tx_cnt++; } February 26, 2020 Veton Kpuska 124 DMAx_IRQ_STATUS Register *pDMA7_IRQ_STATUS *pDMA7_IRQ_STATUS|= |=0x0001; 0x0001; February 26, 2020 Veton Kpuska

125 Event Handling UART Receive Event Handling Functions /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priority for UART receive *pSIC_IAR1 = 0xF3FFFFFF; //Assign ISR to this interrupts register_handler(ik_ivg10, receive_isr); //Unmask the UART receive interrupt *pSIC_IMASK = 0x00004000; } /******************************************************** UART receive interrupt service routine ********************************************************/

EX_INTERRUPT_HANDLER(receive_isr) { *pDMA6_IRQ_STATUS |= DMA_DONE; //clear the interrupt rx_cnt++; } February 26, 2020 Veton Kpuska 127 System Event Mapping February 26, 2020 Veton Kpuska 128 Initialization of Interrupts

If the default assignments are acceptable, then interrupt initialization involves only: 1. 2. 3. Initialization of the core Event Vector Table (EVT) vector address entries. Why is this needed? Initialization of the IMASK register Unmasking the specific peripheral interrupts in SIC_IMASK that the system requires February 26, 2020 Veton Kpuska 129

Event Handling Functions /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priority for UART receive *pSIC_IAR1 = 0xF3FFFFFF; //Assign ISR to this interrupts register_handler(ik_ivg10, receive_isr); //Unmask the UART receive interrupt *pSIC_IMASK = 0x00004000; } /******************************************************** UART receive interrupt service routine ********************************************************/ EX_INTERRUPT_HANDLER(receive_isr) { *pDMA6_IRQ_STATUS |= DMA_DONE; //clear the interrupt rx_cnt++; }

February 26, 2020 Veton Kpuska 130 System Interrupt Assignment Register *pSIC_IAR1 *pSIC_IAR1 == 0xF3FFFFFF; 0xF3FFFFFF; 0xf3ffffff = 1111 0xf3ffffff = 1111 0011 0011 1111 1111 1111 1111 1111 1111 1111

1111 1111 1111 1111 1111 DMA6 DMA6(UART (UARTRX) RX) February 26, 2020 Veton Kpuska 131 Servicing Interrupts /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priorities for UART transmit *pSIC_IAR1 = 0x3FFFFFFF

//Assign ISR to this interrupt See register_handler(ik_ivg10, transmit_isr); //Unmask the UART transmit interrupt *pSIC_IMASK = 0x00008000; Slide System Event Mapping } /******************************************************** UART transmit interrupt service routine ********************************************************/ EX_INTERRUPT_HANDLER(transmit_isr) { *pDMA7_IRQ_STATUS |= DMA_DONE; //clear the interrupt tx_cnt++; } February 26, 2020

Veton Kpuska 132 Registering an ISR typedef enum { ik_emulation, ik_reset, ik_nmi, ik_exception, ik_global_int_enable, ik_hardware_err, ik_timer, ik_ivg7, ik_ivg8, ik_ivg9, ik_ivg10, ik_ivg11, ik_ivg12, ik_ivg13, ik_ivg14, ik_ivg15

} interrupt_kind; ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn, int enable); February 26, 2020 Veton Kpuska 133 Event Handling Functions /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priority for UART receive *pSIC_IAR1 = 0xF3FFFFFF; //Assign ISR to this interrupts register_handler(ik_ivg10, receive_isr); //Unmask the UART receive interrupt *pSIC_IMASK = 0x00004000; }

Unmasking Unmaskingof ofthe theInterrupt Interruptby bysetting setting corresponding bits in SIC_IMASK corresponding bits in SIC_IMASKregister. register. /******************************************************** UART receive interrupt service routine ********************************************************/ EX_INTERRUPT_HANDLER(receive_isr) { *pDMA6_IRQ_STATUS |= DMA_DONE; //clear the interrupt

rx_cnt++; } February 26, 2020 Veton Kpuska 134 SIC_IMASK Register *pSIC_IMASK *pSIC_IMASK == 0x00004000; 0x00004000; 0x00008000 = 0000 0x00008000 = 0000 0000 0000 0000 0000 0000 0000 0100 0000

0000 0000 0100 0000 0000 0000 DMA DMAInterrupt Interrupt UART UARTRX RX February 26, 2020 Veton Kpuska 135 Servicing Interrupts UART RX DMA Interrupt Status Registers

February 26, 2020 Veton Kpuska 137 Event Handling Functions /******************************************************** Function to setup interrupts ********************************************************/ void setup_interrupts() { //Setup priority for UART receive *pSIC_IAR1 = 0xF3FFFFFF; //Assign ISR to this interrupts register_handler(ik_ivg10, receive_isr); //Unmask the UART receive interrupt *pSIC_IMASK = 0x00004000; } /******************************************************** UART receive interrupt service routine ********************************************************/

EX_INTERRUPT_HANDLER(receive_isr) { *pDMA6_IRQ_STATUS |= DMA_DONE; //clear the interrupt rx_cnt++; } February 26, 2020 Veton Kpuska 138 DMAx_IRQ_STATUS Register *pDMA6_IRQ_STATUS *pDMA6_IRQ_STATUS|= |=0x0001; 0x0001; February 26, 2020 Veton Kpuska

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