EECS 252 Graduate Computer Architecture Lec XX - TOPIC

EECS 252 Graduate Computer Architecture Lec XX - TOPIC

CSE 820 Graduate Computer Architecture Lec 7 Instruction Level Parallelism Based on slides by David Patterson Review from Last Time 4 papers: All about where to draw line between HW and SW IBM set foundations for ISAs since 1960s 8-bit byte Byte-addressable memory (as opposed to word-addressable memory) 32-bit words Two's complement arithmetic (but not the first processor) 32-bit (SP) / 64-bit (DP) Floating Point format and registers Commercial use of microcoded CPUs Binary compatibility / computer family B5000 very different model: HLL only, stack, Segmented VM IBM paper made case for ISAs good for microcoded processors leading to CISC Berkeley paper made the case for ISAs for pipeline + cache micrprocessors (VLSI) leading to RISC Who won RISC vs. CISC? VAX is dead. Intel 80x86 on desktop, RISC in embedded, Servers x86 and RISC 2 Outline ILP Compiler techniques to increase ILP Loop Unrolling Static Branch Prediction Dynamic Branch Prediction Overcoming Data Hazards with Dynamic Scheduling (Start) Tomasulo Algorithm

Conclusion 3 Recall from Pipelining Review Pipeline CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls Ideal pipeline CPI: measure of the maximum performance attainable by the implementation Structural hazards: HW cannot support this combination of instructions Data hazards: Instruction depends on result of prior instruction still in the pipeline Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps) 4 Instruction Level Parallelism Instruction-Level Parallelism (ILP): overlap the execution of instructions to improve performance 2 approaches to exploit ILP: 1) Rely on hardware to help discover and exploit the parallelism dynamically (e.g., Pentium 4, AMD Opteron, IBM Power) , and 2) Rely on software technology to find parallelism, statically at compile-time (e.g., Itanium 2) Next 4 lectures on this topic 5 Instruction-Level Parallelism (ILP) Basic Block (BB) ILP is quite small BB: a straight-line code sequence with no branches except to the entry and no branches out except at the exit average dynamic branch frequency 15% to 25% => 4 to 7 instructions execute between a pair of branches Plus instructions in BB likely to depend on each other To obtain substantial performance enhancements, we must exploit ILP across

multiple basic blocks Simplest: loop-level parallelism to exploit parallelism among iterations of a loop. E.g., for (i=1; i<=1000; i=i+1) x[i] = x[i] + y[i]; 6 Loop-Level Parallelism Exploit loop-level parallelism by unrolling loop either by 1. dynamic via branch prediction or 2. static via loop unrolling by compiler (Another way is vectors, to be covered later) Determining instruction dependence is critical to Loop Level Parallelism If 2 instructions are parallel, they can execute simultaneously in a pipeline of arbitrary depth without causing any stalls (assuming no structural hazards) dependent, they are not parallel and must be executed in order, although they may often be partially overlapped 7 Data Dependence and Hazards InstrJ is data dependent (aka true dependence) on InstrI: 1. InstrJ tries to read operand before InstrI writes it I: add r1,r2,r3 J: sub r4,r1,r3 2. or InstrJ is data dependent on InstrK which is dependent on InstrI If two instructions are data dependent, they cannot execute simultaneously or be completely overlapped Data dependence in instruction sequence data dependence in source code effect of original data dependence must be preserved If data dependence caused a hazard in pipeline, called a Read After Write (RAW) hazard

8 ILP and Data Dependencies, Hazards HW/SW must preserve program order: order instructions would execute in if executed sequentially as determined by original source program Dependences are a property of programs Presence of dependence indicates potential for a hazard, but actual hazard and length of any stall is property of the pipeline Importance of the data dependencies 1) indicates the possibility of a hazard 2) determines order in which results must be calculated 3) sets an upper bound on how much parallelism can possibly be exploited HW/SW goal: exploit parallelism by preserving program order only where it affects the outcome of the program 9 Name Dependence #1: Anti-dependence Name dependence: when 2 instructions use same register or memory location, called a name, but no flow of data between the instructions associated with that name; 2 versions of name dependence InstrJ writes operand before InstrI reads it I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Called an anti-dependence by compiler writers. This results from reuse of the name r1 If anti-dependence caused a hazard in the pipeline, called a Write After Read (WAR) hazard 10 Name Dependence #2: Output dependence InstrJ writes operand before InstrI writes it. I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Called an output dependence by compiler writers. This also results from the reuse of name r1 If anti-dependence caused a hazard in the pipeline, called a Write After Write (WAW) hazard Instructions involved in a name dependence can execute simultaneously if name used in instructions is changed so instructions do not conflict Register renaming resolves name dependence for registers

Renaming can be done either by compiler or by HW 11 Control Dependencies Every instruction is control dependent on some set of branches, and, in general, these control dependencies must be preserved to preserve program order if p1 { S1; }; if p2 { S2; } S1 is control dependent on p1, and S2 is control dependent on p2 but not on p1. 12 Control Dependence Ignored Control dependence need not be preserved willing to execute instructions that should not have been executed, thereby violating the control dependences, if can do so without affecting correctness of the program Instead, 2 properties critical to program correctness are 1) exception behavior and 2) data flow 13 Exception Behavior Preserving exception behavior any changes in instruction execution order must not change how exceptions are raised in program ( no new exceptions) Example: DADDU R2,R3,R4 BEQZ R2,L1 LW R1,0(R2) L1: (Assume branches not delayed) Problem with moving LW before BEQZ?

14 Data Flow Data flow: actual flow of data values among instructions that produce results and those that consume them branches make flow dynamic, determine which instruction is supplier of data Example: DADDU R1,R2,R3 BEQZ R4,L DSUBU R1,R5,R6 L: OR R7,R1,R8 OR depends on DADDU or DSUBU? Must preserve data flow on execution 15 Administrivia Paper: Limits of instruction-level parallelism, by David Wall, Nov 1993 Read pages 1-35 (> of paper is figures) In your comments, rank in order of importance alias analysis, branch prediction, jump prediction, register renaming, and speculative execution In your comments, mention what are limits to this study of limits of ILP? 16 Computers in the News Who said this? A. Jimmy Carter, 1979 B. Bill Clinton, 1996 C. Al Gore, 2000 D. George W. Bush, 2006 "Again, I'd repeat to you that if we can remain the most competitive nation in the world, it will benefit the worker here in America. People have got to understand, when we talk about spending your taxpayers' money on research and development, there is a correlating benefit, particularly to your children. See, it takes a while for some of the investments that are

being made with government dollars to come to market. I don't know if people realize this, but the Internet began as the Defense Department project to improve military communications. In other words, we were trying to figure out how to better communicate, here was research money spent, and as a result of this sound investment, the Internet came to be. The Internet has changed us. It's changed the whole world." 17 Outline ILP Compiler techniques to increase ILP Loop Unrolling Static Branch Prediction Dynamic Branch Prediction Overcoming Data Hazards with Dynamic Scheduling (Start) Tomasulo Algorithm Conclusion 18 Software Techniques: Example This code, add a scalar to a vector: for (i=1000; i>0; i=i1) x[i] = x[i] + s; Assume following latencies for all examples Ignore delayed branch in these examples Instruction producing result FP ALU op FP ALU op Load double Load double Integer op Instruction using result

Another FP ALU op Store double FP ALU op Store double Integer op Latency in cycles 4 3 1 1 1 stalls between in cycles 3 2 1 0 0 19 FP Loop: Where are the Hazards? First translate into MIPS code: -To simplify, assume 8 is lowest address Loop: L.D F0,0(R1) ;F0=vector element ADD.D F4,F0,F2 ;add scalar from F2 S.D 0(R1),F4 ;store result DADDUI R1,R1,-8 ;decrement pointer 8B (DW) BNEZR1,Loop ;branch R1!=zero 20 FP Loop Showing Stalls 1 Loop: L.D 2 stall 3 ADD.D 4 stall

5 stall 6 S.D 7 DADDUI 8 stall 9 BNEZ Instruction producing result FP ALU op FP ALU op Load double F0,0(R1) ;F0=vector element F4,F0,F2 ;add scalar in F2 0(R1),F4 ;store result R1,R1,-8 ;decrement pointer 8B (DW) ;assumes cant forward to branch R1,Loop ;branch R1!=zero Instruction using result Another FP ALU op Store double FP ALU op Latency in clock cycles 3 2 1 9 clock cycles: Rewrite code to minimize stalls? 21 Revised FP Loop Minimizing Stalls 1 Loop: L.D F0,0(R1) 2 DADDUI R1,R1,-8 3 ADD.D F4,F0,F2 4

stall 5 stall 6 7 S.D 8(R1),F4 BNEZ R1,Loop ;altered offset when move DSUBUI Swap DADDUI and S.D by changing address of S.D Instruction producing result FP ALU op FP ALU op Load double Instruction using result Another FP ALU op Store double FP ALU op Latency in clock cycles 3 2 1 7 clock cycles, but just 3 for execution (L.D, ADD.D,S.D), 4 for loop overhead; How make faster? 22 Unroll Loop Four Times (straightforward way) 1 Loop:L.D 3 ADD.D 6 S.D 7

L.D 9 ADD.D 12 S.D 13 L.D 15 ADD.D 18 S.D 19 L.D 21 ADD.D 24 S.D 25 DADDUI 26 BNEZ F0,0(R1) F4,F0,F2 0(R1),F4 F6,-8(R1) F8,F6,F2 -8(R1),F8 F10,-16(R1) F12,F10,F2 -16(R1),F12 F14,-24(R1) F16,F14,F2 -24(R1),F16 R1,R1,#-32 R1,LOOP 1 cycle stall Rewrite loop to stalls? 2 cycles stall minimize ;drop DSUBUI & BNEZ ;drop DSUBUI & BNEZ ;drop DSUBUI & BNEZ ;alter to 4*8

27 clock cycles, or 6.75 per iteration (Assumes R1 is multiple of 4) 23 Unrolled Loop Detail Do not usually know upper bound of loop Suppose it is n, and we would like to unroll the loop to make k copies of the body Instead of a single unrolled loop, we generate a pair of consecutive loops: 1st executes (n mod k) times and has a body that is the original loop 2nd is the unrolled body surrounded by an outer loop that iterates (n/k) times For large values of n, most of the execution time will be spent in the unrolled loop 24 Unrolled Loop That Minimizes Stalls 1 Loop:L.D 2 L.D 3 L.D 4 L.D 5 ADD.D 6 ADD.D 7 ADD.D 8 ADD.D 9 S.D 10 S.D 11 S.D 12 DSUBUI 13 S.D 14 BNEZ

F0,0(R1) F6,-8(R1) F10,-16(R1) F14,-24(R1) F4,F0,F2 F8,F6,F2 F12,F10,F2 F16,F14,F2 0(R1),F4 -8(R1),F8 -16(R1),F12 R1,R1,#32 8(R1),F16 ; 8-32 = -24 R1,LOOP 14 clock cycles, or 3.5 per iteration 25 5 Loop Unrolling Decisions Requires understanding how one instruction depends on another and how the instructions can be changed or reordered given the dependences: 1. Determine loop unrolling useful by finding that loop iterations were independent (except for maintenance code) 2. Use different registers to avoid unnecessary constraints forced by using same registers for different computations 3. Eliminate the extra test and branch instructions and adjust the loop termination and iteration code 4. Determine that loads and stores in unrolled loop can be interchanged by observing that loads and stores from different iterations are independent Transformation requires analyzing memory addresses and finding that they do not refer to the same address 5. Schedule the code, preserving any dependences needed to yield the same result as the original code 26 3 Limits to Loop Unrolling 1. Decrease in amount of overhead amortized with each extra unrolling Amdahls Law

2. Growth in code size For larger loops, concern it increases the instruction cache miss rate 3. Register pressure: potential shortfall in registers created by aggressive unrolling and scheduling If not be possible to allocate all live values to registers, may lose some or all of its advantage Loop unrolling reduces impact of branches on pipeline; another way is branch prediction 27 Static Branch Prediction Lecture 3 showed scheduling code around delayed branch To reorder code around branches, need to predict branch statically when compile Simplest scheme is to predict a branch as taken More accurate scheme predicts branches using profile information collected from earlier runs, and modify prediction based on last run: Misprediction Rate Average misprediction = untaken branch frequency = 34% SPEC 25% 22% 18% 20% 15%

15% 12% 11% 12% 9% 10% 4% 5% 10% 6% 0% t s cc ot s t so g e s n pr re eq p m es co Integer li uc d do r ea r d p

o 2 d j c o dl dr u2 y m s h Floating Point 28 Dynamic Branch Prediction Why does prediction work? Underlying algorithm has regularities Data that is being operated on has regularities Instruction sequence has redundancies that are artifacts of way that humans/compilers think about problems Is dynamic branch prediction better than static branch prediction? Seems to be There are a small number of important branches in programs which have dynamic behavior 29 Dynamic Branch Prediction Performance = (accuracy, cost of misprediction) Branch History Table: Lower bits of PC address index table of 1-bit values Says whether or not branch taken last time No address check Problem: in a loop, 1-bit BHT will cause two mispredictions (avg is 9 iterations before exit): End of loop case, when it exits instead of looping as before First time through loop on next time through code, when it predicts exit instead of looping 30

Dynamic Branch Prediction Solution: 2-bit scheme where change prediction only if get misprediction twice T Predict Taken NT T Red: stop, not taken T NT Green: go, taken Predict Not T Adds hysteresis to decision making process Taken Predict Taken NT Predict Not Taken NT 31 BHT Accuracy Mispredict because either: Wrong guess for that branch Got branch history of wrong branch when index the table Misprediction Rate 4096 entry table: 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 18%

12% 10% 5% t o cc ot t s g n es r eq p es Integer 9% 9% 9% 5% 0% li uc ce i ice d p p s s do 1% pp 0 0 sa 7 3 p a fp

ri x n t a m 32 Floating Point Correlated Branch Prediction Idea: record m most recently executed branches as taken or not taken, and use that pattern to select the proper n-bit branch history table In general, (m,n) predictor means record last m branches to select between 2m history tables, each with n-bit counters Thus, old 2-bit BHT is a (0,2) predictor Global Branch History: m-bit shift register keeping T/NT status of last m branches. Each entry in table has m n-bit predictors. 33 Correlating Branches (2,2) predictor Behavior of recent branches selects between four predictions of next branch, updating just that prediction Branch address 4 2-bits per branch predictor Prediction 2-bit global branch history 34 Accuracy of Different Schemes 4096 Entries 2-bit BHT Unlimited Entries 2-bit BHT 1024 Entries (2,2) BHT

18% 16% 14% 12% 11% 10% 8% 6% 6% 5% 6% 6% Unlimited entries: 2-bits/entry li eqntott expresso gcc fpppp matrix300 4,096 entries: 2-bits per entry spice 1% 0% doducd 1% tomcatv 2%

0% 5% 4% 4% nasa7 Frequency of Mispredictions 20% 1,024 entries (2,2) 35 Tournament Predictors Multilevel branch predictor Use n-bit saturating counter to choose between predictors Usual choice between global and local predictors 36 Tournament Predictors Tournament predictor using, say, 4K 2-bit counters indexed by local branch address. Chooses between: Global predictor 4K entries index by history of last 12 branches (212 = 4K) Each entry is a standard 2-bit predictor Local predictor Local history table: 1024 10-bit entries recording last 10 branches, index by branch address The pattern of the last 10 occurrences of that particular branch used to index table of 1K entries with 3-bit saturating counters 37 Comparing Predictors (Fig. 2.8) Advantage of tournament predictor is ability to select the right predictor for a particular branch Particularly crucial for integer benchmarks. A typical tournament predictor will select the global predictor almost 40% of the time for the SPEC integer benchmarks and less than 15% of the time for the SPEC FP benchmarks

38 Pentium 4 Misprediction Rate (per 1000 instructions, not per branch) 14 13 6% misprediction rate per branch SPECint (19% of INT instructions are branch) 12 12 2% misprediction rate per branch SPECfp (5% of FP instructions are branch) 11 11 10 9 9 8 7 7 6 5 5 4 3 2 1 1

0 0 0 m es a 17 7. ap pl u 17 3. d m gr i 17 2. im sw 17 1. is e cr af ty w up w 16 8. SPECint2000 18 6. m

cf 18 1. gc c 17 6. vp r 17 5. gz ip 0 16 4. Branch mispredictions per 1000 I nstructions 13 SPECfp2000 39 Branch Target Buffers (BTB) Branch target calculation is costly and stalls the instruction fetch. BTB stores PCs the same way as caches The PC of a branch is sent to the BTB When a match is found the corresponding Predicted PC is returned If the branch was predicted taken, instruction fetch continues at the returned predicted PC Branch Target Buffers Dynamic Branch Prediction Summary Prediction becoming important part of execution Branch History Table: 2 bits for loop accuracy Correlation: Recently executed branches correlated with next branch Either different branches (GA) Or different executions of same branches (PA)

Tournament predictors take insight to next level, by using multiple predictors usually one based on global information and one based on local information, and combining them with a selector In 2006, tournament predictors using 30K bits are in processors like the Power5 and Pentium 4 Branch Target Buffer: include branch address & prediction 42 Outline ILP Compiler techniques to increase ILP Loop Unrolling Static Branch Prediction Dynamic Branch Prediction Overcoming Data Hazards with Dynamic Scheduling (Start) Tomasulo Algorithm Conclusion 43 Advantages of Dynamic Scheduling Dynamic scheduling - hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior It handles cases when dependences unknown at compile time it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve It allows code that compiled for one pipeline to run efficiently on a different pipeline It simplifies the compiler Hardware speculation, a technique with significant performance advantages, builds on dynamic scheduling (next lecture) 44

HW Schemes: Instruction Parallelism Key idea: Allow instructions behind stall to proceed DIVD ADDD SUBD F0,F2,F4 F10,F0,F8 F12,F8,F14 Enables out-of-order execution and allows out-oforder completion (e.g., SUBD) In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) Will distinguish when an instruction begins execution and when it completes execution; between 2 times, the instruction is in execution Note: Dynamic execution creates WAR and WAW hazards and makes exceptions harder 45 Dynamic Scheduling Step 1 Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue Split the ID pipe stage of simple 5-stage pipeline into 2 stages: IssueDecode instructions, structural hazards check for Read operandsWait until no data hazards, then read operands 46 A Dynamic Algorithm: Tomasulos For IBM 360/91 (before caches!) Long memory latency Goal: High Performance without special compilers Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations This led Tomasulo to try to figure out how to get more effective registers

renaming in hardware! Why Study 1966 Computer? The descendants of this have flourished! Alpha 21264, Pentium 4, AMD Opteron, Power 5, 47 Tomasulo Algorithm Control & buffers distributed with Function Units (FU) FU buffers called reservation stations; have pending operands Registers in instructions replaced by values or pointers to reservation stations(RS); called register renaming ; Renaming avoids WAR, WAW hazards More reservation stations than registers, so can do optimizations compilers cant Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs Avoids RAW hazards by executing an instruction only when its operands are available Load and Stores treated as FUs with RSs as well Integer instructions can go past branches (predict taken), allowing FP ops beyond basic block in FP queue 48 Tomasulo Organization FP Registers From Mem FP Op Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Add1 Add2 Add3

Mult1 Mult2 Reservation Stations FP FP FPadders adders FPmultipliers multipliers Common Data Bus (CDB) To Mem 49 Reservation Station Components Op: Operation to perform in the unit (e.g., + or ) Vj, Vk: Value of Source operands Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) Note: Qj,Qk=0 => ready Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register result statusIndicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. 50 Three Stages of Tomasulo Algorithm 1. Issueget instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Executeoperate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write resultfinish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available Normal data bus: data + destination (go to bus)

Common data bus: data + source (come from bus) 64 bits of data + 4 bits of Functional Unit source address Write if matches expected Functional Unit (produces result) Does the broadcast Example speed: 3 clocks for Fl .pt. +,-; 10 for * ; 40 clks for / 51 Instruction stream Tomasulo Example Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result Load1 Load2 Load3

Register result status: Clock 0 No No No 3 Load/Buffers Reservation Stations: Time Name Busy Add1 No Add2 No FU count Add3 No down Mult1 No Mult2 No Busy Address Op S1 Vj S2 Vk RS Qj RS Qk 3 FP Adder R.S. 2 FP Mult R.S. F0 F2 F4 F6

F8 F10 F12 ... FU Clock cycle counter 52 F30 Tomasulo Example Cycle 1 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write

Issue Comp Result 1 Reservation Stations: Time Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Register result status: Clock 1 FU Busy Address Load1 Load2 Load3 Op S1 Vj S2 Vk RS Qj RS Qk F0 F2 F4 F6 F8

Yes No No 34+R2 F10 F12 ... Load1 53 F30 Tomasulo Example Cycle 2 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2

Exec Write Issue Comp Result 1 2 Reservation Stations: Time Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Register result status: Clock 2 FU Busy Address Load1 Load2 Load3 Op S1 Vj S2 Vk RS Qj RS Qk F0 F2 F4 F6

F8 Load2 Yes Yes No 34+R2 45+R3 F10 F12 ... Load1 Note: Can have multiple loads outstanding 54 F30 Tomasulo Example Cycle 3 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2

R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes MULTD Mult2 No Register result status: Clock 3 FU F0 Busy Address 3 S1 Vj Load1 Load2 Load3 S2 Vk RS Qj Yes

Yes No 34+R2 45+R3 F10 F12 RS Qk R(F4) Load2 F2 Mult1 Load2 F4 F6 F8 ... Load1 Note: registers names are removed (renamed) in Reservation Stations; MULT issued Load1 completing; what is waiting for Load1? 55 F30 Tomasulo Example Cycle 4 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10

ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 Reservation Stations: Busy Address 3 4 4 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS

Qk F2 F4 F6 F8 No Yes No 45+R3 F10 F12 Time Name Busy Op Add1 Yes SUBD M(A1) Load2 Add2 No Add3 No Mult1 Yes MULTD R(F4) Load2 Mult2 No Register result status: Clock 4 FU F0 Mult1 Load2 ... M(A1) Add1 Load2 completing; what is waiting for Load2? 56 F30

Tomasulo Example Cycle 5 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 Reservation Stations: Busy Address 3 4 4 5

Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op 2 Add1 Yes SUBD M(A1) M(A2) Add2 No Add3 No 10 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 5 FU F0 Mult1 M(A2) No No No

F10 F12 ... M(A1) Add1 Mult2 Timer starts down for Add1, Mult1 57 F30 Tomasulo Example Cycle 6 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3

4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op 1 Add1 Yes SUBD M(A1) M(A2) Add2 Yes ADDD M(A2) Add1 Add3 No 9 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status:

Clock 6 FU F0 Mult1 M(A2) Add2 No No No F10 F12 ... Add1 Mult2 Issue ADDD here despite name dependency on F6? 58 F30 Tomasulo Example Cycle 7 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0

F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 Busy Address 4 5 Load1 Load2 Load3 7 S1 Vj S2 Vk RS Qj RS Qk F2

F4 F6 F8 Time Name Busy Op 0 Add1 Yes SUBD M(A1) M(A2) Add2 Yes ADDD M(A2) Add1 Add3 No 8 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 7 FU F0 No No No Mult1 M(A2) Add2 F10 F12 ... Add1 Mult2 Add1 (SUBD) completing; what is waiting for it? 59 F30 Tomasulo Example Cycle 8 Instruction status: Instruction LD

F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3

7 8 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No 2 Add2 Yes ADDD (M-M) M(A2) Add3 No 7 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 8 FU F0 Mult1 M(A2) No No No

F10 F12 ... Add2 (M-M) Mult2 60 F30 Tomasulo Example Cycle 9 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4

5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No 1 Add2 Yes ADDD (M-M) M(A2) Add3 No 6 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD

M(A1) Mult1 Register result status: Clock 9 FU F0 Mult1 M(A2) No No No F10 F12 ... Add2 (M-M) Mult2 61 F30 Tomasulo Example Cycle 10 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0

F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 4 5 7 8 Busy Address Load1 Load2 Load3 10 S1 Vj S2 Vk RS Qj RS Qk

F2 F4 F6 F8 Time Name Busy Op Add1 No 0 Add2 Yes ADDD (M-M) M(A2) Add3 No 5 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 10 FU F0 No No No Mult1 M(A2) F10 F12 ... Add2 (M-M) Mult2 Add2 (ADDD) completing; what is waiting for it? 62 F30 Tomasulo Example Cycle 11 Instruction status: Instruction

LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2

Load3 7 8 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No 4 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 11 FU F0

Mult1 M(A2) No No No F10 F12 ... (M-M+M)(M-M) Mult2 Write result of ADDD here? All quick instructions complete in this cycle! 63 F30 Tomasulo Example Cycle 12 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6

F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4

F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No 3 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 12 FU F0 Mult1 M(A2) No No No F10 F12 ... (M-M+M)(M-M) Mult2 64 F30 Tomasulo Example Cycle 13 Instruction status: Instruction LD F6 LD F2 MULTD F0

SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8

10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No 2 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 13 FU F0 Mult1 M(A2) No No No

F10 F12 ... (M-M+M)(M-M) Mult2 65 F30 Tomasulo Example Cycle 14 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3

4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No

Add2 No Add3 No 1 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 14 FU F0 Mult1 M(A2) No No No F10 F12 ... (M-M+M)(M-M) Mult2 66 F30 Tomasulo Example Cycle 15 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6

j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 15 7 4 5 Load1 Load2 Load3 10 11 S1 Vj S2

Vk RS Qj RS Qk F2 F4 F6 F8 8 Time Name Busy Op Add1 No Add2 No Add3 No 0 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 15 FU F0 Mult1 M(A2) No No No F10 F12 ...

(M-M+M)(M-M) Mult2 Mult1 (MULTD) completing; what is waiting for it? 67 F30 Tomasulo Example Cycle 16 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations:

3 4 15 7 4 5 16 8 Load1 Load2 Load3 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 40 Mult2 Yes DIVD M*F4 M(A1) Register result status:

Clock 16 FU F0 Busy Address M*F4 M(A2) No No No F10 F12 ... (M-M+M)(M-M) Mult2 Just waiting for Mult2 (DIVD) to complete 68 F30 Faster than light computation (skip a couple of cycles) 69 Tomasulo Example Cycle 55 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j

34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 15 7 4 5 16 8 Load1 Load2 Load3 10 11 S1 Vj S2 Vk

RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 1 Mult2 Yes DIVD M*F4 M(A1) Register result status: Clock 55 FU F0 Busy Address M*F4 M(A2) No No No F10 F12 ... (M-M+M)(M-M) Mult2

70 F30 Tomasulo Example Cycle 56 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 15

7 56 10 4 5 16 8 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk 56 FU F0 F2 F4 F6 F8 M*F4 M(A2) No No No 11 Time Name Busy Op Add1

No Add2 No Add3 No Mult1 No 0 Mult2 Yes DIVD M*F4 M(A1) Register result status: Clock Busy Address F10 F12 ... (M-M+M)(M-M) Mult2 Mult2 (DIVD) is completing; what is waiting for it? 71 F30 Tomasulo Example Cycle 57 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8

k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 15 7 56 10 4 5 16 8 57 11 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk

F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No Mult2 Yes DIVD M*F4 M(A1) Register result status: Clock 56 FU F0 Busy Address M*F4 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Result Once again: In-order issue, out-of-order execution and out-of-order completion. 72 Why can Tomasulo

overlap iterations of loops? Register renaming Multiple iterations use different physical destinations for registers (dynamic loop unrolling). Reservation stations Permit instruction issue to advance past integer control flow operations Also buffer old values of registers - totally avoiding the WAR stall Other perspective: Tomasulo building data flow dependency graph on the fly 73 Tomasulos scheme offers 2 major advantages 1. Distribution of the hazard detection logic distributed reservation stations and the CDB If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB If a centralized register file were used, the units would have to read their results from the registers when register buses are available 2. Elimination of stalls for WAW and WAR hazards 74 Tomasulo Drawbacks Complexity delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 in CA:AQA 2/e, but not in silicon! Many associative stores (CDB) at high speed Performance limited by Common Data Bus Each CDB must go to multiple functional units high capacitance, high wiring density Number of functional units that can complete per cycle limited to one! Multiple CDBs more FU logic for parallel assoc stores Non-precise interrupts! We will address this later 75

And In Conclusion #1 Leverage Implicit Parallelism for Performance: Instruction Level Parallelism Loop unrolling by compiler to increase ILP Branch prediction to increase ILP Dynamic HW exploiting ILP Works when cant know dependence at compile time Can hide L1 cache misses Code for one machine runs well on another 76 And In Conclusion #2 Reservations stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards Allows loop unrolling in HW Not limited to basic blocks (integer units gets ahead, beyond branches) Helps cache misses as well Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation 360/91 descendants are Intel Pentium 4, IBM Power 5, AMD Athlon/Opteron, 77

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