Iasdfasdfsad - UCSB

Iasdfasdfsad - UCSB

2010 IEEE Device Research Conference, June 21-23, Notre Dame, Indiana III-V FET Channel Designs for High Current Densities and Thin Inversion Layers Mark Rodwell University of California, Santa Barbara Coauthors: W. Frensley: University of Texas, Dallas S. Steiger, S. Lee, Y. Tan, G. Hegde, G. Klimek Network for Computational Nanotechnology, Purdue University E. Chagarov, L. Wang, P. Asbeck, A. Kummel, University of California, San Diego T. Boykin University of Alabama, Huntsville J. N. Schulman The Aerospace Corporation, El Segundo, CA. Acknowledgements: Herb Kroemer (UCSB), Bobby Brar (Teledyne) Art Gossard (UCSB), John Albrecht (DARPA) [email protected] 805-893-3244, 805-893-5705 fax Thin, high current density III-V FET channels InGaAs, InAs FETs THz & VLSI need high current low m* high velocities FET scaling for speed requires increased charge density low m* low charge density Density of states bottleneck (Solomon & Laux IEDM 2001) For < 0.6 nm EOT, silicon beats III-Vs Open the bottle ! low transport mass high vcarrier multiple valleys or anistropic valleys high DOS Use the L valleys. Simple FET Scaling Goal: double transistor bandwidth when used in any circuit reduce 2:1 all capacitances and all transport delays keep constant all resistances, voltages, currents gate-source, gate-drain fringing capacitances:

0.15-0.25 fF/m C gd / Wg ~ must increase gate capacitance/area g m / Wg ~ v (C gs / LgWg ) C gs / Wg (Cgs / Wg Lg ) Lg must reduce gate length C gs , f / Wg ~ To double speed, we must double ( g m / Wg ) , ( I D / Wg ), (C gs / LgWg ), ns . FET Scaling Laws LG Changes required to double device / circuit bandwidth. laws in constant-voltage limit: FET parameter gate length current density (mA/m), gm (mS/m) channel 2DEG electron density electron mass in transport direction gate-channel capacitance density dielectric equivalent thickness channel thickness channel density of states source & drain contact resistivities Current densities should double Charge densities must double change decrease 2:1 increase 2:1 increase 2:1 constant increase 2:1 decrease 2:1 decrease 2:1 increase 2:1 decrease 4:1

gate width WG Semiconductor Capacitances Must Also Scale (Vgs Vth ) cox ( unidirectional motion) cdepth / Tinversion ( E f Ewell ) / q cdos q 2 gm* / 2 2 channel charge qns cdos (V f Vwell ) q( E f Ewell ) ( gm* / 2 2 ) Inversion thickness & density of states must also both scale. Calculating Current: Ballistic Limit Natori Channel Fermi voltage voltage applied to cdos determines Fermi velocity v f through E f qV f m * v 2f / 2 mean electron velocity v (4 / 3 )v f Channel charge : s cdos V f V c cdos cequiv cequiv cdos V gs Vth cdos q 2 gm * / 2 2 cdos ,o g ( m * / mo ) , where g is the # of band minima mA Vgs Vth g (m * / mo )1 / 2

J 84 3/ 2 m 1 V 1 ( cdos ,o / cox ) g (m * / mo ) 3/ 2 Do we get highest current with high or low mass ? Drive current versus mass, # valleys, and EOT mA Vgs Vth J K1 84 m 1 V normalized drive current K 1 0.35 3/ 2 , where K1 InGaAs <--> InP g m* mo 1 (c * dos, o / cequiv ) g ( m / mo ) Si

3/ 2 g=2 g=1 0.3 0.25 cequiv ( 1/cox 1/cdepth ) 1 SiO2 /EOT 0.2 0.3 nm 0.4 nm 0.15 0.1 0.05 1/ 2 0.6 nm EOT=1.0 nm EOT includes the wavefunction depth term (mean wavefunction depth* SiO2 /semiconductor ) 0 0.01 0.1 m*/m o 1 InGaAs MOSFETs: superior Id to Si at large EOT. InGaAs MOSFETs: inferior Id to Si at small EOT. Solomon / Laux Density-of-States-Bottleneck III-V loses to Si.

Transit delay versus mass, # valleys, and EOT Lg 1 Volt Qch ch K 2 7 ID 2.52 10 cm/s Vgs Vth 1/ 2 * m where K 2 m0 EOT=1.0 nm 1.5 1/ 2 1/ 2 0.6 nm 1 nm 2 Normalized transit delay K * cdos,o m 1 g ceq mo 0.4 nm

0.6 nm 0.4 nm 1 cequiv ( 1/cox 1/csemi ) 1 SiO2 /EOT g=1, isotropic bands 0.5 g=2, isotropic bands EOT includes wavefunction depth term (mean wavefunction depth*SiO2 /semiconductor ) 0 0 0.05 0.1 0.15 0.2 0.25 m*/m 0.3 0.35 o Low m* gives lowest transit time, lowest Cgs at any EOT. 0.4 Low effective mass also impairs vertical scaling Shallow electron distribution needed for high Id, high gm / Gds ratio, low drain-induced barrier lowering. 2 * 2 Energy of Lth well state L / m Twell .

For thin wells, only 1st state can be populated. For very thin wells, 1st state approaches L-valley. Only one vertical state in well. Minimum ~ 3 nm well thickness. Hard to scale below 10-16 nm Lg. III-V Band Properties, normal {100} Wafer X valley material substrate m* / mo material substrate 0.045 In 0.5Ga 0.5As InP 0.026 InAs InP 0.067 GaAs GaAs --Si Si ml / mo X valley mt / mo 1.29 1.13 1.30 0.92 0.19 0.16 0.22 0.19 L

L valley E x E 0.83 eV 0.87 eV 0.47 eV (negative) ml / mo mt / mo E L E 1.23 0.062 0.47 eV 0.65 0.050 0.57 eV 1.90 0.075 0.28 eV L - valley transverse masses are comparable to valleys Consider instead: valleys in {111} Wafer L X valley material substrate m* / mo material substrate

0.045 In 0.5Ga 0.5As InP 0.026 InAs InP 0.067 GaAs GaAs --Si Si ml / mo X valley mt / mo 1.29 1.13 1.30 0.92 0.19 0.16 0.22 0.19 L valley E x E 0.83 eV 0.87 eV 0.47 eV (negative) ml / mo mt / mo E L E 1.23 0.062 0.47 eV 0.65

0.050 0.57 eV 1.90 0.075 0.28 eV Orientation : one L valley has high vertical mass X valleys & three L valleys have moderate vertical mass Valley in {111} wafer: with quantization in thin wells L X valley material substrate m* / mo material substrate 0.045 In 0.5Ga 0.5As InP 0.026 InAs InP 0.067 GaAs GaAs --Si Si ml / mo X valley mt / mo 1.29 1.13 1.30 0.92

0.19 0.16 0.22 0.19 L valley E x E 0.83 eV 0.87 eV 0.47 eV (negative) ml / mo mt / mo E L E 1.23 0.062 0.47 eV 0.65 0.050 0.57 eV 1.90 0.075 0.28 eV Selects L[111] valley; low transverse mass {111} -L FET: Candidate Channel Materials valley material material m* / mo In

material 0.5 Ga 0.5 As In Ga 0.045 0.5 0.5 As GaAs GaAs 0.067 GaSb GaSb 0.039 Ge /m mm l /l mo o 1.23 1.23 1.90 1.90 1.30 1.30 1.58 valley LLvalley Well thickness for / m EEL L EE mm L alignment t /t mo o 0.062 0.47 0.47eV eV 0.062 1 nm (?) 0.075 0.28 0.28eV eV 0.075 2 nm 0.10 0.07eV

eV 0.10 0.07 4 nm 0.08 (negative) - - - =0 eV L=177 meV X[100]= 264 meV X[010] = 337 meV Wavefunctions 3 nm GaAs well AlSb barriers Energy, eV Standard III-V FET: valley in [100] orientation 2 1.5 1 0.5 0 -0.5 -1 X[010] X[100] L -1 L 1st Approach: Use both and L valleys in [111] 2.3 nm GaAs well AlSb barriers [111] orientation

-1 X L[111] L[111] L[111] = 41 meV L[111] (1)= 0 meV L[111] (2)= 84 meV L[111] , etc. =175 meV X=288 meV -1 L[111] Combined -L wells in {111} orientation vs. Si mA V V g m m , where K J K 84 1 (c / c ) g (m / m ) m 1 V 3/ 2 gs th 1 o 1 0.35 GaSb GaAs equiv 1

Si o g=2 0.3 cequiv ( 1/cox 1/csemi ) 1 0.25 SiO2 /EOT 0.2 0.3 nm 0.15 0.4 nm 0.1 3/ 2 * dos,o Normalized current density K 1/ 2 * 0.6 nm combined ( -L) transport 0.05 EOT includes the wavefunction depth term (mean wavefunction depth*SiO2 /semiconductor ) 0 0.01 EOT=1.0 nm

0.1 m*/m o 2 nm GaAs /L well g =2, m*/m0=0.07 4 nm GaSb /L well m */m =0.039, m */m =0.1 1 2nd Approach: Use L valleys in Stacked Wells Three 0.66 nm GaAs wells 0.66 nm AlSb barriers [111] orientation L[111](1) = 0 meV L[111](2)= 61 meV L[111](3)= 99 meV =338 meV L[111], etc =232 meV X=284 meV X L[111] L[111] -1 All L[111] -1 Increase in Cdos with 2 and 3 wells 3 C dos,N-well /C dos,1-well 3 wells 2.5

2 2 wells 1.5 1 0.01 1 nm well pitch 2 nm well pitch 3 nm well pitch 0.1 m*/m 1 o 3 High Current Density (111) GaAs/AlSb Designs 2 1.5 1 0.5 0 -0.5 -1 Charge density, 1/cm 3 Wavefunctions Energy, eV (100) orientation 2 s 2.3 nm GaAs well AlSb barriers 3 nm GaAs well AlSb barriers X[010]

X[100] L L Two 0.66 nm GaAs wells 0.66 nm AlSb barriers X L[111] L[111] L[111] -1 Three 0.66 nm GaAs wells 0.66 nm AlSb barriers X L[111] L[111] X L[111] L[111] L[111] -1 -1 All L[111] both L[111] -1 20 1 10 19 8 10

19 6 10 19 4 10 19 2 10 0 0 10 12 N (1/cm ) (111) orientation 8 10 12 6 10 12 4 10 12 2 10 0 L[111] -1 0 1 2 3 4 5 6 7 position, nm 0 1 2 3 4 5 6 7 position, nm -1 -1 -1 0 1 2 3 4 5 6 7 position, nm -1 0 1 2 3 4 5 6 7

position, nm L valleys filling 0 0 0 -0.2 -0.1 0 0.1 0.2 0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.2 -0.1 0 0.1 0.2 0.3 (V -V ), V (V -V ), V (V -V ), V (V -V ), V gs th gs th gs th gs th Concerns Nonparabolic bands reduce bound state energies Failure of effective mass approximation:1-2 nm wells 1-2 monolayer fluctuations in growth scattering collapse in mobility Purdue Confirmation Purdue Confirmation Steiger, Klimeck, Boykin Ryu, Lee, Hegde, Tan 1-D FET array = 2-D FET with high transverse mass

2-D FET 1-D Array FET Weak coupling narrow transverse-mode energy distribution high density of states 3rd Approach: High Current Density L-Valley MQW FINFETs 8 2.5 nm well pitch Drain current, mA/m 7 6 V -V =0.3 V gs 5 3 5 nm well pitch 2 1 EOT includes wavefunction depth term 0 0.01 valley energies Emin,i qVmin,i th 4 (mean wavefunction depth* 2 2 2 * 2i 2m W 0.3 nm EOT 0.6 nm EOT current I i

SiO2 / 0.1 m*/mo semiconductor ) 1 gq 2 V f Vmin,i charge : Qch gl 2m*qV f Vmin,i gate voltage :Vgs V f Qch / Cox i 4th Approach: {110} Orientation Anisotropic Bands P. Asbeck transport L [111], L[11 1 ] : moderate vertical mass valleys populate High in - plane mass perpendicular to transport high density of states Low in - plane mass parallel to transport high carrier velocity L [1 1 1], [ 1 11] : low vertical mass depopulate High in - plane mass parallel to transport low carrier velocity Challenge: only moderate energy separation between desired and undesired valleys. Anisotropic bands, e.g. {110} mA Vgs Vth J K1 84 m 1 V 3/ 2 , where K1 normalized drive current K 1

0.6 1 (c g=2, m / mo ) 3/ 2 0 /m =0.5 perpendicular 0 cequiv ( 1/cox 1/csemi ) 1 SiO2 /EOT 0.3 Transport in {110} oriented L valleys EOT=1.0 nm 0.2 0.1 1/ 2 || / cequiv ) g (m m perpendicular 0.6 nm 0.4 dos ,o 1/ 2

g=2, m /m =0.7 perpendicular 0 g=2, m /m =0.6 0.3 nm 0.4 nm 0.5 g (m1/ 2 / mo1/ 2 ) EOT includes wavefunction depth term (mean wavefunction depth* / 0 0.01 SiO2 semiconductor ) 0.1 m*/m 1 o GaAs and Ge {110} MOSFETs with L - valley transport GaAs : n 2, m t / mo 0.075, ml / mo 1.9 Ge : n 2, m t / mo 0.081, ml / mo 1.58 THz FET scaling: with & without increased DOS Gate length nm

50 35 25 18 13 9 Gate barrier EOT nm 1.2 0.83 0.58 0.41 0.29 0.21 well thickness nm 8.0 5.7 4.0 2.8 2.0 1.4 S/D resistance m 210 150

100 74 53 37 effective mass *m0 0.05 0.05 0.05 0.08 0.08 0.08 1 1 1 1.4 1 1 2 1 1 2.8 1 2 4 1 3 5.7 1

3 # band minima canonical fixed DOS stepped # 2500 f 4000 2500 1500 1500 max f , GHz 2000 canonical scaling stepped # of bands transport only , GHz 3000 f Scaled FET performance: fixed vs. increasing DOS 3000 fmax 2000 1000 500

500 0 2.5 0 1000 SCFL static divider clock rate, GHz drain current density, mA/m 1000 3500 mA/m VLSI metric 2 1.5 1 0.5 200 mV gate overdrive 0 0 10 20 30 40 gate length, nm 50 60 SCFL divider speed 800 600 400 200 0

0 10 20 30 40 gate length, nm 50 Increased density of states needed for high drive current, fast logic @ 16, 11, 8 nm nodes 60 10 nm / 3 THz III-V FETs: Challenges & Solutions gate dielectric: decrease EOT 2:1 To double the bandwidth: S/D access regions: decrease resistivity 2:1 S/D regrowth Wistey et al Singisetti et al channel: keep same velocity, but thin channel 2:1 increase density of states 2:1 L (end) Purdue Confirmation Constant - voltage / constant - velocity scaling laws : MOSFET Scaling Laws Changes required for : 1 increased bandwidth in an arbitrary circuit LS/D Lg LS/D

Tox Twell gate source drain parameter gate length Lg , source-drain contact lengths law 1 LS / D (nm) parameter gate-channel capacitance C g ch law 1 [1 / Co x 1 / Csemi 1 / C DOS ] 1 (fF) gate width Wg (nm) 1 transconductance g m ~ C g ch v injection / Lg (mS) 0 equivalent oxide thickness Teq Tox SiO / oxid e 1 1 (nm) dielectric capacitance Co x SiO LgWg / Teq (fF) gate-source, gate-drain fringing capacitances C gs, f Wg , C g d Wg (fF) 1 S/D access resistances R s , Rd ( )

0 S/D contact resistivity Rs / Wg , Rd / Wg ( m ) 1 2 2 inversion thickness Tinv ~ Twell / 2 (nm) 1 S/D contact resistivity c ( m 2 ) 2 semiconductor capacitance C semi semi LgWg / Tinv (fF) 1 drain current I d ~ g m (V g s Vth ) (mA) 0 DOS capacitance C DOS q 2 nm * LgWg / 2 2 (fF) 1 drain current density ( mA/ m ) 1 electron density n s ( cm -2 ) 1 temperature rise (one device, K) ~ Wg 1 2.0 nm GaAs well, AlAs barriers, on {111} GaAs Bound state energy, eV

1.2 1 valley 0.8 0.6 0.4 L(l) valley 0.2 0 -10 10 -9 10 well thickness, meters 10 -8 2 nm well : and L(l) minima both populated. : m * / mo 0.067 * L(l) : mlateral / mo 0.075 low m* high carrier ve locity two band minima doubles cdos 2 nm well good electrosta tics at ~ 5 - 7 nm Lg . GaSb well, AlSb barriers, on {110} GaSb GaSb well, AlSb barriers, on (110) GaSb Bound state energy, eV 0.6 0.5 L [111], L[11-1] 0.4

X [100], X[010] X [001] 0.3 L [1-11], L[-111] 0.2 0.1 0 -10 10 -9 10 well thickness, meters 10 -8

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