Karnaugh Maps (k maps) - NPRU

Karnaugh Maps (k maps) - NPRU

Karnaugh Maps (K maps) What are Karnaugh1 maps? Karnaugh maps provide an alternative way of simplifying logic circuits. Instead of using Boolean algebra simplification techniques, you can transfer logic values from a Boolean statement or a truth table into a Karnaugh map. The arrangement of 0's and 1's within the map helps you to visualise the logic relationships between the variables and leads directly to a simplified Boolean statement. Named for the American electrical engineer Maurice Karnaugh. 1 Karnaugh maps Karnaugh maps, or K-maps, are often used to simplify logic problems with 2, 3 or 4 variables. Cell = 2n ,where n is a number of variables For the case of 2 variables, we form a map consisting of 2 2=4 cells as shown in Figure A B 0 1 A B 0 0 AB A B 0 00 1 A B A B 1

01 Maxterm A 1 0 1 10 11 B 2 3 0 1 0 1 AB A B AB AB Minterm Karnaugh maps 3 variables Karnaugh map Cell = 23=8 C AB 00 01 0 0 2 10 6 4 A B C A BC ABC AB C 1

1 11 3 7 5 A B C A BC ABC AB C Karnaugh maps 4 variables Karnaugh map CD AB 00 01 11 10 0 4 12 8 1 5 13 9 3 7 15 11 2 6 14

10 00 01 11 10 Karnaugh maps The Karnaugh map is completed by entering a '1(or 0) in each of the appropriate cells. Within the map, adjacent cells containing 1's (or 0s) are grouped together in twos, fours, or eights. Example 2-variable Karnaugh maps are trivial but can be used to introduce the methods you need to learn. The map for a 2-input OR gate looks like this: A 0 1 B A Y B A B Y 0 0 0 0 1 1 1 0 1 1

1 1 1 0 1 1 1 B A+B A Example A B C Y 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0

1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 AC C AB 00 0 1 1 1 01 11 10 1 1 1

B B AC Exercise Let us use Karnaugh map to simplify the follow function. F1 = m0+m2+m3+m4+m5+m6+m7 F2 = m0+m1+m2+m5+m7 Answer Exercise Given the truth table, find the simplified SOP and POS form. A B C Y 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1

0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 Exercise Design two-level NAND-gate logic circuit from the follow timing diagram. A B C D F Dont care term CD AB 00 01 11 10

X 00 01 11 10 AD X 1 X X X X Exercise Design logic circuit that convert a 4-bits binary code to Excess-3 code A B C D W X Y Z 0 0 0 0 0 0 1 1 0

0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1

1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0

0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 x x x x 1 0 1 1 x x x x

1 1 0 0 x x x x 1 1 0 1 x x x x 1 1 1 1 1 1 0 1 x X X X X x X x

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