Microprocessor System Design Processor Timing

Microprocessor System Design Processor Timing

Microprocessor System Design Programmable Interrupt Controller Outline

Interrupts in PC Interrupts and calls 8259 PIC Programming 8259 Interfacing 8259 in PC

What is Interrupt 8086/88 Interrupts

256 Interrupts. Types 00 . FF. Type is provided in a specified timing. Interrupt Vector Table

Answering an Interrupt Save status FR, IP, CS

Service the interrupt Interrupt service routing (ISR) or Interrupt handler Based on Interrupt vector number From Interrupt vector table

Four bytes for every interrupt: CS:IP Return to original position by IRET Difference with Call

1. CALL FAR can jump to any location (1M range) 2. Hardware interrupts can come at any time. 3. Interrupts are maskable.

4. After CALL only CS:IP is saved 5. End of routine: RETF vs. IRET. Interrupt Categories Hardware interrupts:

Only 3 pin, but how 256 interrupt? INTR (in), NMI (in), and INTA (out) INTR can be masked by CLI / STI Active high. 80x86 finished instruction.

Push FR, CS, IP NMI: INT 02.

Software interrupts INT nn Example: INT 21H (DOS functions)

Interrupt and Flags Predefined Interrupts INT 00 (divide error)

INT 01 (single step) Set Trap flag (how?) PUSHF, POP AX, Trace in debug

INT 02 (NMI) INT 03 (breakpoint) INT 04 (signed number overflow) INT) instruction Examine Interrupt vector table.

Examine INT 12H (size of conventional RAM in AX) 8259 Control Word (initialization)

ICW1, ICW2 ICW3, ICW4

Example Masking and Prioritization OCW (operation command word)

Programming OCWs OCW3 8259 in PC XT

ICW1: 13H ICW2: 08H ICW3: 09H

Interrupt Sources in PC Sources of NMI 8259s in AT

IRQ9 Instead of IRQ2 Interrupts (Summary)

Edge Triggered and Interrupt Sharing Level triggered mode: IRQ line should be brought down before EOI. Edge triggered mode: noise on IRQ lines

might cause false interrupts. New computer and busses. Level triggered. Interrupt sharing.

Recently Viewed Presentations