Worst Case Analysis of Electronics Using Parameter Design

Worst Case Analysis of Electronics Using Parameter Design Techniques by Mr. Andrew G. Bell & Mrs. Catherine M. Vincent ITT Industries A/CD Fort Wayne, Indiana WCA - 1 Worst Case Analysis of Electronics Using Parameter Design Techniques Introduction ITT Aerospace/Communications (A/CD) has facilities in Fort Wayne, Indiana and Clifton, New Jersey that employees 1,976 people. This presentation is based on a Parameter Design Technique used on a space project power supply worse case analysis within the Fort Wayne headquarters. WCA - 2 Worst Case Analysis of Electronics Using Parameter Design Techniques Introduction ITT A/CD products include the U.S. Army SINCGARS and U.K. BOWMAN tactical communication system, voice data switches, data entry terminals, fiber optics transmission systems, ground to air radios used by the Federal Aviation Administration (FAA), and a family of secure communications terminals: space-based navigation and atmospheric remote sensing payloadsGPS, Alpha, GOES Imager/Sounder, AVHRR and HIRS Instruments. WCA - 3 Worst Case Analysis of Electronics Using Parameter Design Techniques Background Classical Worst Case Analysis has been used to demonstrate electronic design robustness over the years on numerous space and communication programs at ITT A/CD. The amount of time (computer time and set up time) it takes to complete a WCA can vary greatly based upon the complexity of the design and performance being measured. This variance can be compounded by a simulation failure requiring engineering intervention or the need to execute multi-run simulations. An alternate Parameter Design Technique approach which requires fewer simulations has been successfully used at ITT A/CD to demonstrate a similar quality measurement in far less time. WCA - 4 Worst Case Analysis of Electronics Using Parameter Design Techniques Objectives Compare the Classical Worst Case Analysis approach to the alternate Parameter Design Technique by analysis of the maximum group delay of a 4 pole transitional ButterworthThompson lowpass filter. All simulations were performed on an UltraSPARC-II 400MHz Sun UNIX Workstation. If a circuits robustness can be demonstrated using a technique that produces similar quality measurement relative to the classical techniques there could be: from an engineering standpoint - significant time savings. from a customer standpoint - a cost savings from a managerial standpoint - similar design risk in less time and money.

WCA - 5 Worst Case Analysis of Electronics Using Parameter Design Techniques Approach Using Analog Workbench build a circuit simulation model for a simple 4 pole transitional Butterworth-Thompson lowpass filter. Using classical worst case analysis techniques, predict the circuits worst case group delay performance and measure the simulation time. Use a Parameter Design Technique to predict the circuits worst case performance. Select important noise factors Select appropriate orthogonal array and run experiments Evaluate the simulation results using an analysis of means Determine appropriate confirmation run Compare Parameter Design Technique results to the classical approach. WCA - 6 Worst Case Analysis of Electronics Using Parameter Design Techniques Classical Approach Components are assigned Gaussian distributions for variation. Tolerance all components and run an EVA Sensitivity/Worst Case and Monte Carlo Analyzes that measure the variation in group delay WCA - 7 Worst Case Analysis of Electronics Using Parameter Design Techniques Alternate Approach Parameter Design Technique In our case, we selected component groupings based upon knowledge of the circuits operation. This reduced the number of noise factors down to six. Then we added the load resistance. Select important noise factors brainstorm with others on what is important group terms if possible Noise Factors 1 2 A B C1 & C2 R1 & R2 (min) (min) Select C1 & appropriate C2 R1 & R2 (max) (max) C D

R3 C3 & C4 (min) (min) orthogonal array R3 C3 & C4 (max) (max) E R4 & R5 (min) R4 & R5 (max) F R6 (min) R6 (max) G RL (min) RL (max) Simulations Run A B C D E F G ortho1 1 1 1 1 1 1 1 1 ortho2 2 1 1 1

2 2 2 2 ortho3 3 1 2 2 1 1 2 2 ortho4 4 1 2 2 2 2 1 1 ortho5 5 2 1 2 1 2 1 2 ortho6 6 2 1 2 2 1

2 1 ortho7 7 2 2 1 1 2 2 1 ortho8 8 2 2 1 2 1 1 2 WCA - 8 The L8 Orthogonal Array was selected. It allows for us to test two values for each noise factor. In our example, we selected minimum and maximum values of the factors to be equal to the minimum and maximum values of the components based upon the tolerance of each part. Worst Case Analysis of Electronics Using Parameter Design Techniques Alternate Approach Parameter Design Technique Built and ran eight simulation circuits that measured the group delay. WCA - 9 Worst Case Analysis of Electronics Using Parameter Design Techniques Results Parameter Design Technique Simulations Run

A B C D E F G Results (usec) ortho1 1 1 1 1 1 1 1 1 34.22 ortho2 2 1 1 1 2 2 2 2 35.75 ortho3 3 1 2 2 1 1 2 2

34.75 ortho4 4 1 2 2 2 2 1 1 35.79 ortho5 5 2 1 2 1 2 1 2 37.43 ortho6 6 2 1 2 2 1 2 1 38.09 ortho7 7 2 2 1 1 2

2 1 37.51 ortho8 8 2 2 1 2 1 1 2 38.13 WCA - 10 The raw data for the eight runs was collected and placed into a table. The results show that the group delay of the filter varied between 38.13 sec and 34.22 sec. Total simulation time was 8 seconds. Worst Case Analysis of Electronics Using Parameter Design Techniques Analysis - Using the Analysis of Means Parameter Design Technique Simulations Run A B C D E F G Results (usec) ortho1 1 1 1 1 1 1

1 1 34.22 ortho2 2 1 1 1 2 2 2 2 35.75 ortho3 3 1 2 2 1 1 2 2 34.75 ortho4 4 1 2 2 2 2 1 1 35.79 C 3.64E+01 3.65E+01 ortho5 5 2 1

2 1 2 1 2 37.43 D 3.60E+01 3.69E+01 ortho6 6 2 1 2 2 1 2 1 38.09 E 3.63E+01 3.66E+01 ortho7 7 2 2 1 1 2 2 1 37.51 F 3.64E+01 3.65E+01 ortho8 8 2 2 1 2 1 1 2

38.13 confirmation 9 2 2 2 2 2 2 2 An Analysis of Means (ANOM) is performed on the results to determine which confirmation run might produce the greatest amount of group delay. WCA - 11 AVE (1) AVE (2) A 3.51E+01 3.78E+01 B 3.64E+01 3.65E+01 G 3.64E+01 3.65E+01 Worst Case Analysis of Electronics Using Parameter Design Techniques Analysis - Factor Plots Parameter Design Technique A B C1 & C2 C R1 & R2 39 39 39 38 38 38 37 37 37 36 36 36

35 35 35 34 E 2 1 F R4 & R5 1 2 G R6 39 39 39 38 38 38 37 37 37 36 36 36 35 35 35 34 34 1 WCA - 12 2 2 RL 34 1 2 C3 & C4

39 38 37 36 35 34 34 34 1 D R3 1 2 1 2 In this case, the proposed confirmation run that produces the greatest group delay is when all noise factors are at their maximum. Worst Case Analysis of Electronics Using Parameter Design Techniques Analysis - using Classical Worst Case Analysis EVA Sensitivity/Worst Case result of 38.75 sec required 16 seconds of total simulation time. Monte Carlo worst case result of 37.7 sec required 16 minutes and 40 seconds total simulation time. WCA - 13 Worst Case Analysis of Electronics Using Parameter Design Techniques Confirmation With the factors changed for the confirmation run the predicted worst case group delay is about 38.57 sec. Total simulation time was 1 second. WCA - 14 Worst Case Analysis of Electronics Using Parameter Design Techniques Conclusions Simulations Run A B C D E F

G Results (usec) ortho1 1 1 1 1 1 1 1 1 34.22 ortho2 2 1 1 1 2 2 2 2 35.75 ortho3 3 1 2 2 1 1 2 2 34.75 ortho4 4 1 2 2 2

2 1 1 35.79 ortho5 5 2 1 2 1 2 1 2 37.43 ortho6 6 2 1 2 2 1 2 1 38.09 ortho7 7 2 2 1 1 2 2 1 37.51 ortho8 8 2 2

1 2 1 1 2 38.13 confirmation 9 2 2 2 2 2 2 2 38.57 Monte Carlo 37.70 EVA 38.75 This is not to suggest that we abandon the classical approaches because sometimes they will produce results that are more accepted by our customers and may show true worst case performance. However, in some cases an alternate approach may be acceptable to the customer and more cost effective. WCA - 15 In this example, the alternate Parameter Design Technique produced a worst case result that was greater than the 1000 run Monte Carlo but less than EVA. Total simulation times Parameter Design Technique = 9 sec EVA Sensitivity/Worst Case = 16 sec Monte Carlo = 16 min and 40 sec Worst Case Analysis of Electronics Using Parameter Design Techniques Acknowledgements We would like to thank Eric Smith and George Adamczyk for allowing us to write this paper. WCA - 16