Part I: Introduction

Part I: Introduction

VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi 1 Workshop Outline Introduction to the workshop and setting targets Combinational and sequential logic Max+plusII package features and usage guide

Hands on VHDL (Lab1) VHDL design units Designing a simple circuit and its testing (Lab2) Design of a sequential logic circuit (lab3) Design project 2 Some Example Designs A multiplexer is a circuit that has several inputs and only one output line One of the inputs is selected using selection lines for onward connection with the output In VHDL, multiplexers can be achieved using conditional assignment statements 3

A 4-to-1 Multiplexer library ieee; use ieee.std_logic_1164.all; entity mux4to1 is port (Sel:in std_logic_vector(0 to 1); A:in std_logic_vector(0 to 3); Y:out std_logic);

end mux4to1; architecture mux1 of mux4to1 is begin Y <= A(0) when Sel = 00 else A(1) when Sel = 01 else A(2) when Sel = 10 else A(3) when others; end mux1; 4 An 8-Bit Register With Asynchronous Reset

library ieee; use ieee.std_logic_1164.all; entity reg8 is port (D:in std_logic_vector(7 downto 0); reset,clk:in std_logic; Q:out std_logic_vector(7 downto 0); end reg8; architecture myreg of reg8 is begin process(reset,clk) begin if reset=0 then Q<= 00000000;

elsif clkevent and clk=1 then Q<=D; end if; end process; end myreg; 5 Generate Statements You can generate several components using for..generate statements in VHDL For example, derive a 16-to-1 Multiplexer from the given 4-to-1 Multiplexer The source code is given 6 Generate Statements

library ieee; use ieee.std_logic_1164.all; entity mux16to1 is port (Sel:in std_logic_vector(0 to 3); A:in std_logic_vector(0 to 15); Y:out std_logic); end mux16to1; architecture mux2 of mux16to1 is

Begin Signal m:std_logic_vector(0 to 3); Component mux4to1 is Port (Sel:in std_logic_vector(0 to 1); A:in std_logic_vector(0 to 3); Y:out std_logic); end component; 7 Generate Statement Begin G1: for I in 0 to 3 generate Muxes: mux4to1 port map (Sel(0 to 1), A(4*i to 4*i+3), m(i)); End generate; Mux5: mux4to1 port map (Sel(2 to 3), m(0 to 3), Y); End structure; 8

Design Project Using the 4-bit comparator designed earlier, develop a circuit that contains a comparator and a 4-bit register. The register will be loaded with a 4-bit number with the rising edge of the clock. Another four bit number will be applied directly to the other input of the comparator. Show the results 9

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