Pci-cfd - Na60

Pci-cfd - Na60

A PCI Card for Readout in High Energy Physics Experiments Michele Floris1,2, Gianluca Usai1,2, Davide Marras2, Andr David3 1) Dipartimento di Fisica, Universit degli studi di Cagliari, Italy. 2) INFN, Sezione di Cagliari, Italy. 3) CERN, Geneva, Switzerland 2003 IEEE Nuclear Science Symposium October 19 -25 Portland, Oregon, USA Outline Motivations and requirements Implementation Applications F L E X I B I L I T Y NA60 DAQ Muon

Spectrometer Quartz fiber Zero Degree Calorimeter Silicon strip Beam Tracker Silicon pixel Vertex Telescope Alice Muon tracking chambers test system October 19 - 25 2003 2003 IEEE NSS, Portland, Oregon, USA 2 Motivation & design requirements NA60 Experiment DAQ Fast development NA60 is a running experiment Flexibility Readout Partitions Dipole field 2.5 T TARGET BOX

BEAM BEAM TELESCOPE TRACKER October 19 - 25 2003 IC MUON FILTER of 4 different detectors ~1m TARGET AREA Muon filter Tracking MUON SPECTROMETER MWPCs Toroidal Magnet Fe wall ZDC and Trigger Quartz Blade hodoscopes 2003 IEEE NSS, Portland, Oregon, USA

3 NA60 readout system PCI based system: Good performances / low cost Readout of several different detectors General purpose PCI readout card Detector specific mezzanine DET MEZZANINE PCI Card DAQ PC NA60 DAQ scheme NA60 readout is spill-buffered DAQ handshake with readout system October 19 - 25 2003 2003 IEEE NSS, Portland, Oregon, USA

burst burst interburst events - trigger 4 The PCI-CFD 64 MB SDRA M Altera EP20K100, BGA package flexibility reliability 1-Wire Unique ID ~ 2 months from the first schematic to a working prototype PLX 9030 (PCI Target) Fast October development 19 - 25 2003

PLX EEPROM 2003 IEEE NSS, Portland, Oregon, USA Tristate buffer (JTAG input) PMC connectors (not fully compliant IEEE 1386.1) 5 PCI-CFD RAM CTRL SDRAM REGs USER APPL. CTRL MEZZANINE Only these blocks change between different applications PCI interface

PLX 9030 October 19 - 25 2003 2003 IEEE NSS, Portland, Oregon, USA 6 JTAG Configuration MEZZANINE The PLX has some general purpose I/O, we used them to implement a JTAG interface The JTAG chain can be extended to the mezzanine, using a jumper CONN EPROM PLX TRISTATE October 19 - 25 2003 A tristate buffer is used to multiplex JTAG inputs

FPGA CFD and mezzanine FPGAs can be JTAG programmed via PCI bus 2003 IEEE NSS, Portland, Oregon, USA 7 Software Linux software has been developed PLX Eeprom programming PCI JTAG configuration Driver Sample code PCI memory is seen as an extension of main memory! open (/dev/cfdX, O_RDWR); mmap (... ... , REGISTERS/MEMORY);

memcpy (in, out, size); October 19 - 25 2003 2003 IEEE NSS, Portland, Oregon, USA Interfacing with (DAQ) software is extremely easy! 8 NA60 VME-like/FERA interfaces Very simple mezzanine Level conversion ECL/NIM => TTL Protocol itself implemented in PCI Card FPGA R/O of 3 detectors implemented 2 different protocols (RMH/FERA) BURST BUSY TRIGGER trigger start_read

encode dflag PCI data end_of_read Card October 19 - 25 2003 Protocol control signals & data 2003 IEEE NSS, Portland, Oregon, USA 9 NA60 Pixel readout Pixel detector Almost 800k channels Several configurable parameters Complex mezzanine Readout control zero suppression (FPGA) Temporary data

storage (FIFOs) See also N16-5 at this conference F I F o GOL chip PILOT chip PCI-CFD hybrid with assemblies NA60 Pixel readout contd Serial link PCI-CFD => mez. Detector & electronics configuration 101101110010 Command register Start register FIFO Output register

October 19 - 25 2003 2003 IEEE NSS, Portland, Oregon, USA 11 Alice Test system 1 fully equipped slat chamber readout AD DSP emulation in FPGA Custom DAQ software October 19 - 25 2003 See also N26-35 at this conference 2003 IEEE NSS, Portland, Oregon, USA 12 Conclusions PCI bus offers very attractive features High Performances Low cost Easy interfacing with SW

Using hardware cores PCI cards can be developed with little effort Flexibility: FPGA Mezzanines Several different applications: VME-like, FERA interfaces Custom applications: pixel readout, DSP emulation October 19 - 25 2003 2003 IEEE NSS, Portland, Oregon, USA 13

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