GODSON-3B1500 Mostafa Koraei A presentation for DSP Implementation

GODSON-3B1500 Mostafa Koraei A presentation for DSP Implementation

GODSON-3B1500 Mostafa Koraei A presentation for DSP Implementation Course Main Reference : Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-Core Processor on ISSCC 2013 HISTORY OF GODSON

BLX IC Design Corporation founded in 2002 in Beijing BLX is fabless Fabricated in STMicroelectronics Loongson processors with Linux are strategic for china Based on MIPS64 Prof Hu Weiwu [1,2] LOONGSON1 OR GODSON-232

Instruction set is MIPS32 Internal architecture is different 32 bit , 266 MHz O.18 micron CMOS 8 KB Data/Instruction Cache 200 MFLOPS In 2007 ICT bought MIPS license [1,2]

LOONGSON2 64 bit architecture 500 MHz Loongson2E

4 way superscalar out of order execution 2 ALU , 2 FPU Separate 64/64 KB instruction and data L1 caches On chip 512 KB L2 cache Max 7 w at 1 GHz Loongson2F DDRII memory controller Max 4 W at 1 GHz [2,3] LOONGSON2 Loongson2F Software-controlled dynamic power management

Loongson2G 1 GHz 65 nm 3 Watt 64KB+64KB L1 (four-way) 1 MB L2 cache Loongson2H SATA, USB, GMAC controller [2,3] [3]

GODSON 3 Scalable architecture at 2010 65 nm ,1 GHz , Quad core ,Max 15 Watt 64 entry register file Separated 16 entry reservation station for fixed point and floating point

Reconfigurable core GS464 or Gstera Dynamic L2 cache migration DMA reconfigurable to data is from or to L2 or main memory [4,6] MICRO ARCHITECTURE TB : Branch Target Buffer HT: Branch History Table GU: Address Generation Unit LB: Instruction Translation look aside Buffer TLB: Data Translation look aside Buffer [6]

RECONFIGURABILITY [6] DIE PHOTO OF GODSON-3B1500 GODSON 3B1500 8 core ,32 nm , 1.35 GHz ,40 Wat

172.8 GFLOPS Cu-layer high- metal-gate (HKMG) 1.14 billion transistors in 182.5mm2 35% power-efficiency improvement [1,5] MODIFICATIONS OF THE MEMORY HIERARCHY last-level cache (LLC) is increased from

4MB to 8MB a 4-way 128KB private victim cache in each core low-cost asynchronous FIFO between every core and uncore to isolate cores in voltage and frequency [1] MODIFICATION IN I/O Update P2P HyperTransport (HT) from 1 to 2

Memory access speed from DDRIII 800 to DDRII 1200 [1] CLOCKING SCHEME globally asynchronous locally synchronous (GALS) External rclk 33 MHz Global clock glck 200 MHz DFS Dynamic Frequency Scaling 1.5 GHz Node Clock 1 GHz DCDL : digital-controlled delay lines

[5] MEMORY INTERFACE Two 64b 153.6Gb/s on-die termination (ODT) impedance (60-120 range with 5 step)

Dynamic output slew-rate control dynamic off-chip driver (OCD) impedance (34-40 range with 1 step [1] HYPERTRANSPORT Bandwidth of 22.4GB/s Up to 2.8Gb/pin/s

BER of less than 10^-15 (CDR)simple direct sampling in lowpower mode All-digital DLL-based CDR for high speed [1] HPC WITH GODSON-3A Linpack test results [4] REFERENCES

[1] Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-Core Processor ISSCC 2013 / SESSION 3 / PROCESSORS/ 3.5 [2] Loongson on Wikipedia [3] Godson-2H: a complex low power SOC in 65nm CMOS IEEE 2012 [4] Design and Implementation of BIOS for Godson-3A

Interconnections IEEE 2011 [5] Godson-3B: A 1GHz 40W 8-Core 128GFLOPS Processor in 65nm CMOS ISSCC 2011 / SESSION 4 / ENTERPRISE PROCESSORS & COMPONENTS / 4.4 [6] GODSON-3:A SCALABLE MULTICORE RISCPROCESSORWITHX86 EMULATION IEEE 2009 [7] Microarchitecture and Performance Analysis of Godson-2 SMT Processor IEEE 2006

Recently Viewed Presentations

  • Chapter 18

    Chapter 18

    The temperature range for poaching is 160 to 180. The poaching liquid transfers heat to the food by convection. A properly poached product maintains its shape and delicate texture. Two distinct techniques: Shallow poaching: poaching in a small amount of...
  • SWAN Quarterly Update March 7, 2019 1 March

    SWAN Quarterly Update March 7, 2019 1 March

    SWAN Fiscal Year 2020 Budget. Refer to exhibit pages 28 - 48. Budget summary page 28. RAILS LLSAP Funding Grant page 29. Fee chart pages 40-41. SWAN Library roll call vote performed by Tiffany Verzani, SWAN Board Secretary
  • real-time embedded systems - Arizona State University

    real-time embedded systems - Arizona State University

    Binding of GPIOs to Pins. Example: gpio 26 is bit 10 of the 1st PCAL9535 chip. Each GPIO chip is represented by " struct. gpio_chip " standard methods such as get, set, etc.
  • Aim: How did the Monroe Doctrine Influence the

    Aim: How did the Monroe Doctrine Influence the

    Aim: How did the Monroe Doctrine Influence the Foreign Policy in the United States?Do Now: Copy vocabulary below into your Notebooks. President James Monroe- the 5th President of the U.S. . Monroe . Doctrine- statement of the United States policy...
  • Humanitarian Assistance during the First World War German

    Humanitarian Assistance during the First World War German

    Times Times New Roman Geneva Arial Arial Arial Blank Presentation PowerPoint Presentation German invasion of France: September 1914 Blockade of North Sea, Atlantic & Mediterranean Map of Relief Area of Belgium and Northern France Belgian atrocities: cartoon in Punch Belgian...
  • Child Support: The Next Generation

    Child Support: The Next Generation

    Subconscious looks for facts that support established attitudes, beliefs, and biases. ... Unintended Bias = Unequal Justice. Black men are significantly more likely than white people to: ... Widen Your Circle.
  • A Bicycle Safety Education Program for Parents of Young Children

    A Bicycle Safety Education Program for Parents of Young Children

    A bicycle safety education program for parents of young children. Effectiveness of a tailored intervention to increase factory workers' use of hearing protection. An explanatory model of variables influencing health promotion behaviors in smoking and nonsmoking college students. Balanced analgesia...
  • Blackboard: Assessment Tools

    Blackboard: Assessment Tools

    … a vision for change Andrew Williams Director ILT Support and Development Kingston College The Kingston College experience Medium-sized learning provider Period of reinvention Cautious adopter of ILT and e-learning JISC Pre-inspection ILT Health-check Response New ILT Strategy SMT and...