GODSON-3B1500 Mostafa Koraei A presentation for DSP Implementation
GODSON-3B1500 Mostafa Koraei A presentation for DSP Implementation Course Main Reference : Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-Core Processor on ISSCC 2013 HISTORY OF GODSON
BLX IC Design Corporation founded in 2002 in Beijing BLX is fabless Fabricated in STMicroelectronics Loongson processors with Linux are strategic for china Based on MIPS64 Prof Hu Weiwu [1,2] LOONGSON1 OR GODSON-232
Instruction set is MIPS32 Internal architecture is different 32 bit , 266 MHz O.18 micron CMOS 8 KB Data/Instruction Cache 200 MFLOPS In 2007 ICT bought MIPS license [1,2]
LOONGSON2 64 bit architecture 500 MHz Loongson2E
4 way superscalar out of order execution 2 ALU , 2 FPU Separate 64/64 KB instruction and data L1 caches On chip 512 KB L2 cache Max 7 w at 1 GHz Loongson2F DDRII memory controller Max 4 W at 1 GHz [2,3] LOONGSON2 Loongson2F Software-controlled dynamic power management
GODSON 3 Scalable architecture at 2010 65 nm ,1 GHz , Quad core ,Max 15 Watt 64 entry register file Separated 16 entry reservation station for fixed point and floating point
Reconfigurable core GS464 or Gstera Dynamic L2 cache migration DMA reconfigurable to data is from or to L2 or main memory [4,6] MICRO ARCHITECTURE TB : Branch Target Buffer HT: Branch History Table GU: Address Generation Unit LB: Instruction Translation look aside Buffer TLB: Data Translation look aside Buffer 
RECONFIGURABILITY  DIE PHOTO OF GODSON-3B1500 GODSON 3B1500 8 core ,32 nm , 1.35 GHz ,40 Wat
172.8 GFLOPS Cu-layer high- metal-gate (HKMG) 1.14 billion transistors in 182.5mm2 35% power-efficiency improvement [1,5] MODIFICATIONS OF THE MEMORY HIERARCHY last-level cache (LLC) is increased from
4MB to 8MB a 4-way 128KB private victim cache in each core low-cost asynchronous FIFO between every core and uncore to isolate cores in voltage and frequency  MODIFICATION IN I/O Update P2P HyperTransport (HT) from 1 to 2
 MEMORY INTERFACE Two 64b 153.6Gb/s on-die termination (ODT) impedance (60-120 range with 5 step)
Dynamic output slew-rate control dynamic off-chip driver (OCD) impedance (34-40 range with 1 step  HYPERTRANSPORT Bandwidth of 22.4GB/s Up to 2.8Gb/pin/s
BER of less than 10^-15 (CDR)simple direct sampling in lowpower mode All-digital DLL-based CDR for high speed  HPC WITH GODSON-3A Linpack test results  REFERENCES
 Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-Core Processor ISSCC 2013 / SESSION 3 / PROCESSORS/ 3.5  Loongson on Wikipedia  Godson-2H: a complex low power SOC in 65nm CMOS IEEE 2012  Design and Implementation of BIOS for Godson-3A
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