Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider

Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider

Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider Topologies up to 100 GHz Ekaterina Laskin, Sean T. Nicolson, Sorin P. Voinigescu University of Toronto, Canada Pascal Chevalier, Alain Chantre, Bernard Sautreuil, STMicroelectronics, France Outline Motivation Static divider topology Fabrication technologies Test setup and results Conclusion 10 October 2006

Paper Number 12.3 2/23 Motivation Applications at 80 GHz: Phase-locked loop Radio circuits Comparison of divider topologies Technology benchmark 10 October 2006 Paper Number 12.3 3/23 Static Divider Topology On-chip transformer and matching Toggle flip-flop, 50 output buffer 2 different latch designs implemented 10 October 2006

Paper Number 12.3 4/23 Integrated Transformer primary 30m secondary Stacked design, top 2 metals over substrate 30m square, 1m spacing, 2m metal width 10 October 2006 Paper Number 12.3 5/23 Transformer Model primary k secondary substrate

model Model extracted from geometry using ASITIC - network includes substrate model k = 0.855 is achieved 10 October 2006 Paper Number 12.3 6/23 Input Network Simulation Divider input matched 40 100 GHz Transformer operational up to 100 GHz 10 October 2006 Paper Number 12.3 7/23 Latch Design 1 w/o input EF ECL latch Inductive

peaking No split load Self-biased Resistive input biasing 10 October 2006 Paper Number 12.3 8/23 Latch Design 2 with input EF Double-EF input buffer 10 October 2006 Paper Number 12.3 9/23 Implementation Both dividers fabricated in 2 SiGe processes: 300

250 300 BiCMOS9 200 250 150 fT 100 fT 100 50 50 0

fMAX 200 f MAX 150 BipX 0.1 1 2 JC (mA/ m ) 10 October 2006 10

0 0.1 Paper Number 12.3 1 2 JC (mA/m ) 10 10/23 Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX

10 October 2006 Paper Number 12.3 11/23 Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX 10 October 2006 Paper Number 12.3 12/23 Fabricated Dividers

with input EF w/out input EF BiCMOS9 BipX 10 October 2006 Paper Number 12.3 13/23 Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX

10 October 2006 Paper Number 12.3 14/23 Fabricated Dividers with input EF BiCMOS9 BipX 10 October 2006 w/out input EF 515m 473m 502m 360m 3.3 V

3.3 V 145 mW 122 mW Paper Number 12.3 15/23 Test Setup 0 - 50 GHz: 50 - 75 GHz: 75 - 100 GHz: 10 October 2006 Paper Number 12.3 16/23 Measurement Results

Divider self-oscillation frequency: Divider SOF (GHz) 80 75 BipX2 BipX1 BipX 70 65 60 55 50 45 40 220 Divider with EF Divider w/out EF

BiCMOS9 240 260 280 300 Process f MAX (GHz) 10 October 2006 Paper Number 12.3 17/23 Sensitivity Curves 20 25 C Input Power [dBm]

10 0 -10 -20 BipX, w/o EF BipX, w/ EF BiCMOS9, w/o EF BiCMOS9, w/ EF -30 -40 -50 10 20 30 40 50

60 70 80 90 100 Input Frequency [GHz] 10 October 2006 Paper Number 12.3 18/23 Sensitivity Curves 20 Input Power [dBm] 10

0 -10 -20 25 C 50 C 100 C -30 -40 -50 10 20 30 40 50 60

70 80 90 100 Input Frequency [GHz] 10 October 2006 Paper Number 12.3 19/23 Divider Phase Noise Input 100 GHz -90.4 dBc/Hz @ 100 kHz offset Output

50 GHz -96.4 dBc/Hz @ 100 kHz offset Phase noise -6 dB with frequency halving 10 October 2006 Paper Number 12.3 20/23 Further Improvements 20 MOS-HBT Input Power [dBm] 10 0 -10 HBT only

-20 BiCMOS9, HBT only BiCMOS9, MOS-HBT BipX, HBT only -30 -40 -50 10 20 30 40 50 60 70

80 90 100 Input Frequency [GHz] 10 October 2006 Paper Number 12.3 21/23 Comparison to Previous Work Divider SOF [GHz] 100 [9] 90

[6] 80 This Work [2] 70 [8] 60 50 40 30 100 InP CMOS SiGe This Work [7]

[5] 200 300 400 500 Technology fT [GHz] 10 October 2006 Paper Number 12.3 22/23 Conclusion 2 SiGe static dividers designed and analyzed in 2 technologies Designed divider operates up to 100 GHz Features an integrated transformer operating at 100 GHz Ideal phase noise behaviour

Low power 10 October 2006 Paper Number 12.3 23/23 Thank You 10 October 2006 Paper Number 12.3 24/23 Back-up Slides 10 October 2006 Paper Number 12.3 25/23

50- Output Buffer 10 October 2006 Paper Number 12.3 26/23 BipX Process Splits 300 300 BipX2 250 250 200 200

fMAX 150 100 150 fMAX fT 100 fT 50 0 BipX1 50 0.1 10 October 2006

1 IC (mA) 10 0 0.1 Paper Number 12.3 1 IC (mA) 10 27/23 Measurement Results Divider self-oscillation frequency: Divider SOF (GHz)

80 BipX 75 70 BipX2 65 BipX1 60 55 50 Divider with EF Divider w/out EF BiCMOS9 45

40 170 190 210 230 250 270 Process f T (GHz) 10 October 2006 Paper Number 12.3 28/23 Measurement Results with input EF

BiCMOS9 BipX 10 October 2006 w/out input EF avg= 45.9 GHz avg= 52.03 GHz s.dev.= 1.54 GHz avg= 65.02 GHz avg= 72.43 GHz s.dev.= 2.06 GHz Paper Number 12.3 29/23 Source Phase Noise @ 100GHz

10 October 2006 Paper Number 12.3 30/23 BiCMOS Divider 10 October 2006 Paper Number 12.3 31/23

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