Carnegie Mellon Machine-Level Programming I: Basics CENG331 -

Carnegie Mellon Machine-Level Programming I: Basics CENG331 -

Carnegie Mellon Machine-Level Programming I: Basics CENG331 - Computer Organization Adapted from slides of the textbook: http://csapp.cs.cmu.edu/ Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition Carnegie Mellon Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Arithmetic & logical operations Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 2 Carnegie Mellon Intel x86 Processors Dominate laptop/desktop/server market Evolutionary design Backwards compatible up until 8086, introduced in 1978 Added more features as time goes on Complex instruction set computer (CISC)

Many different instructions with many different formats But, only small subset encountered with Linux programs Hard to match performance of Reduced Instruction Set Computers (RISC) But, Intel has done just that! In terms of speed. Less so for low power. Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 3 Carnegie Mellon Intel x86 Evolution: Milestones Name Date 8086 TransistorsMHz 1978 29K 5-10 First 16-bit Intel processor. Basis for IBM PC & DOS 1MB address space 386 1985 275K 16-33 First 32 bit Intel processor , referred to as IA32 Added flat addressing, capable of running Unix Pentium 4E 2004

125M 2800-3800 First 64-bit Intel x86 processor, referred to as x86-64 Core 2 2006 291M 1060-3500 731M 1700-3900 First multi-core Intel processor Core i7 2008 Four cores Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 4 Carnegie Mellon Intel x86 Processors, cont. Machine Evolution

386 Pentium Pentium/MMX PentiumPro Pentium III Pentium 4 Core 2 Duo Core i7 1985 1993 1997 1995 1999 2001 2006 2008 0.3M 3.1M 4.5M 6.5M 8.2M 42M 291M 731M Added Features Instructions to support multimedia operations Instructions to enable more efficient conditional operations Transition from 32 bits to 64 bits More cores

Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 5 Carnegie Mellon 2015 State of the Art Core i7 Broadwell 2015 Desktop Model 4 cores Integrated graphics 3.3-3.8 GHz 65W Server Model 8 cores Integrated I/O 2-2.6 GHz 45W Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 6 Carnegie Mellon 2019 State of the Art

I9-9900 Coffee Lake architecture 8-cores 3.6 GHz https://en.wikichip.org/wiki/intel/core_i9/i9-9900k Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 7 Carnegie Mellon x86 Clones: Advanced Micro Devices (AMD) Historically AMD has followed just behind Intel A little bit slower, a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies Built Opteron: tough competitor to Pentium 4 Developed x86-64, their own extension to 64 bits Recent Years Intel got its act together Leads the world in semiconductor technology AMD has fallen behind Relies on external semiconductor manufacturer Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition

8 Carnegie Mellon Intels 64-Bit History 2001: Intel Attempts Radical Shift from IA32 to IA64 Totally different architecture (Itanium) Executes IA32 code only as legacy Performance disappointing 2003: AMD Steps in with Evolutionary Solution x86-64 (now called AMD64) Intel Felt Obligated to Focus on IA64 Hard to admit mistake or that AMD is better 2004: Intel Announces EM64T extension to IA32 Extended Memory 64-bit Technology Almost identical to x86-64! All but low-end x86 processors support x86-64 But, lots of code still runs in 32-bit mode Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 9 Carnegie Mellon Our Coverage

IA32 The traditional x86 x86-64 The standard cow> gcc hello.c cow> gcc m64 hello.c Presentation Book covers x86-64 Web aside on IA32 We will only cover x86-64 Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 10 Carnegie Mellon Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Arithmetic & logical operations Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 11 Carnegie Mellon Definitions

Instruction Set Architecture (ISA): The parts of a processor design that one needs to understand or write assembly/machine code. Examples: instruction set specification, registers. Microarchitecture: Implementation of the architecture. Examples: cache sizes and core frequency. Code Forms: Machine Code: The byte-level programs that a processor executes Assembly Code: A text representation of machine code Example ISAs: Intel: x86, IA32, Itanium, x86-64 ARM: Used in almost all mobile phones Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 12 Carnegie Mellon Assembly/Machine Code View CPU Memory Addresses Registers Code Data Stack Data

PC Condition Codes Instructions Programmer-Visible State PC: Program counter Address of next instruction Called RIP (x86-64) Register file Memory Byte addressable array Code and user data Stack to support procedures Heavily used program data Condition codes Store status information about most recent arithmetic or logical operation Used for conditional branching Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 13 Carnegie Mellon Turning C into Object Code Code in files p1.c p2.c Compile with command: gcc Og p1.c p2.c -o p Use basic optimizations (-Og) [New to recent versions of GCC]

Put resulting binary in file p text C program (p1.c p2.c) Compiler (gcc Og -S) text Asm program (p1.s p2.s) Assembler (gcc or as) binary Object program (p1.o p2.o) Linker (gcc or ld) binary Static libraries (.a) Executable program (p) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 14 Carnegie Mellon Compiling Into Assembly C Code (sum.c) long plus(long x, long y); void sumstore(long x, long y, long *dest) { long t = plus(x, y); *dest = t; } Generated x86-64 Assembly sumstore: pushq

movq call movq popq ret %rbx %rdx, %rbx plus %rax, (%rbx) %rbx Obtain with command gcc Og S sum.c Produces file sum.s Warning: Will get very different results on different machines (Linux, Mac OS-X, ) due to different versions of gcc and different compiler settings. Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 15 Carnegie Mellon Assembly Characteristics: Data Types Integer data of 1, 2, 4, or 8 bytes Data values Addresses (untyped pointers) Floating point data of 4, 8, or 10 bytes Code: Byte sequences encoding series of instructions No aggregate types such as arrays or structures Just contiguously allocated bytes in memory

Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 16 Carnegie Mellon Assembly Characteristics: Operations Perform arithmetic function on register or memory data Transfer data between memory and register Load data from memory into register Store register data into memory Transfer control Unconditional jumps to/from procedures Conditional branches Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 17 Carnegie Mellon Object Code Code for sumstore 0x0400595: 0x53 0x48 0x89 0xd3 0xe8 0xf2 0xff 0xff 0xff 0x48

0x89 0x03 0x5b 0xc3 Assembler Total of 14 bytes Each instruction 1, 3, or 5 bytes Starts at address 0x0400595 Translates .s into .o Binary encoding of each instruction Nearly-complete image of executable code Missing linkages between code in different files Linker Resolves references between files Combines with static run-time libraries E.g., code for malloc, printf Some libraries are dynamically linked Linking occurs when program begins execution Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 18 Carnegie Mellon

Machine Instruction Example *dest = t; C Code Store value t where designated by dest movq %rax, (%rbx) Assembly Move 8-byte value to memory Quad words in x86-64 parlance Operands: t: Register %rax dest: Register %rbx *dest: Memory M[%rbx] 0x40059e: 48 89 03 Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition Object Code 3-byte instruction Stored at address 0x40059e 19 Carnegie Mellon Disassembling Object Code Disassembled

0000000000400595 400595: 53 400596: 48 89 400599: e8 f2 40059e: 48 89 4005a1: 5b 4005a2: c3 : d3 ff ff ff 03 push mov callq mov pop retq %rbx %rdx,%rbx 400590 %rax,(%rbx) %rbx Disassembler objdump d sum Useful tool for examining object code Analyzes bit pattern of series of instructions Produces approximate rendition of assembly code Can be run on either a.out (complete executable) or .o file Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 20 Carnegie Mellon Alternate Disassembly Disassembled

Object 0x0400595: 0x53 0x48 0x89 0xd3 0xe8 0xf2 0xff 0xff 0xff 0x48 0x89 0x03 0x5b 0xc3 Dump of assembler code for function sumstore: 0x0000000000400595 <+0>: push %rbx 0x0000000000400596 <+1>: mov %rdx,%rbx 0x0000000000400599 <+4>: callq 0x400590 0x000000000040059e <+9>: mov %rax,(%rbx) 0x00000000004005a1 <+12>:pop %rbx 0x00000000004005a2 <+13>:retq Within gdb Debugger gdb sum disassemble sumstore Disassemble procedure x/14xb sumstore Examine the 14 bytes starting at sumstore Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 21

Carnegie Mellon Meet Gdb Your new friend The GNU Debugger https://www.gnu.org/ software/gdb / Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 22 Carnegie Mellon What Can be Disassembled? % objdump -d WINWORD.EXE WINWORD.EXE: file format pei-i386 No symbols in "WINWORD.EXE". Disassembly of section .text: 30001000 <.text>: 30001000: 55 push %ebp 30001001: 8b ec mov %esp,%ebp Reverse engineering forbidden by 30001003: 6a ff push $0xffffffff Agreement 30001005: 68Microsoft 90 10 00End 30 User push License

$0x30001090 3000100a: 68 91 dc 4c 30 push $0x304cdc91 Anything that can be interpreted as executable code Disassembler examines bytes and reconstructs assembly source Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 23 Carnegie Mellon Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Arithmetic & logical operations Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 24 Carnegie Mellon x86-64 Integer Registers %rax %eax %r8 %r8d %rbx

%ebx %r9 %r9d %rcx %ecx %r10 %r10d %rdx %edx %r11 %r11d %rsi %esi %r12 %r12d %rdi %edi %r13 %r13d %rsp %esp %r14

%r14d %rbp %ebp %r15 %r15d Can reference low-order 4 bytes (also low-order 1 & 2 bytes) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 25 Carnegie Mellon general purpose Some History: IA32 Registers Origin (mostly obsolete) %eax %ax %ah %al accumulate %ecx %cx %ch %cl

counter %edx %dx %dh %dl data %ebx %bx %bh %bl base %esi %si source index %edi %di destination index %esp %sp %ebp %bp

16-bit virtual registers (backwards compatibility) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition stack pointer base pointer 26 Carnegie Mellon Moving Data Moving Data movq Source, Dest: Operand Types Immediate: Constant integer data %rax %rcx %rdx %rbx %rsi %rdi %rsp %rbp Example: $0x400, $-533 Like C constant, but prefixed with $ Encoded with 1, 2, or 4 bytes Register: One of 16 integer registers Example: %rax, %r13 %rN But %rsp reserved for special use Others have special uses for particular instructions Memory: 8 consecutive bytes of memory at address given by register

Simplest example: (%rax) Various other address modes Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 27 Carnegie Mellon movq Operand Combinations Source movq Dest Src,Dest C Analog Imm Reg movq $0x4,%rax Mem movq $-147,(%rax) temp = 0x4; Reg Reg movq %rax,%rdx Mem movq %rax,(%rdx) temp2 = temp1; Mem Reg movq (%rax),%rdx *p = -147;

*p = temp; temp = *p; Cannot do memory-memory transfer with a single instruction Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 28 Carnegie Mellon Simple Memory Addressing Modes Normal (R) Mem[Reg[R]] Register R specifies memory address Aha! Pointer dereferencing in C movq (%rcx),%rax Displacement D(R) Mem[Reg[R]+D] Register R specifies start of memory region Constant displacement D specifies offset movq 8(%rbp),%rdx Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 29 Carnegie Mellon Example of Simple Addressing Modes void swap (long *xp, long *yp) { long t0 = *xp; long t1 = *yp; *xp = t1; *yp = t0;

} Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition swap: movq movq movq movq ret (%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi) 30 Carnegie Mellon Understanding Swap() Memory void swap (long *xp, long *yp) { long t0 = *xp; long t1 = *yp; *xp = t1; *yp = t0; } Register %rdi %rsi %rax %rdx Value xp yp t0 t1

Registers %rdi %rsi %rax %rdx swap: movq movq movq movq ret Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition (%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi) # # # # t0 = *xp t1 = *yp *xp = t1 *yp = t0 31 Carnegie Mellon Understanding Swap() Memory Registers %rdi 0x120 %rsi

0x100 Address 123 0x118 0x110 %rax 0x108 %rdx swap: movq movq movq movq ret 0x120 456 (%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition # # # # 0x100 t0 = *xp t1 = *yp *xp = t1

*yp = t0 32 Carnegie Mellon Understanding Swap() Memory Registers %rdi 0x120 %rsi 0x100 %rax 123 Address 123 0x118 0x110 0x108 %rdx swap: movq movq movq movq ret 0x120 456

(%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition # # # # 0x100 t0 = *xp t1 = *yp *xp = t1 *yp = t0 33 Carnegie Mellon Understanding Swap() Memory Registers %rdi 0x120 %rsi 0x100 %rax 123 %rdx 456

swap: movq movq movq movq ret Address 123 0x120 0x118 0x110 0x108 456 (%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition # # # # 0x100 t0 = *xp t1 = *yp *xp = t1 *yp = t0 34 Carnegie Mellon Understanding Swap() Memory

Registers %rdi 0x120 %rsi 0x100 %rax 123 %rdx 456 swap: movq movq movq movq ret Address 456 0x120 0x118 0x110 0x108 456 (%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition

# # # # 0x100 t0 = *xp t1 = *yp *xp = t1 *yp = t0 35 Carnegie Mellon Understanding Swap() Memory Registers %rdi 0x120 %rsi 0x100 %rax 123 %rdx 456 swap: movq movq movq movq ret

Address 456 0x120 0x118 0x110 0x108 123 (%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition # # # # 0x100 t0 = *xp t1 = *yp *xp = t1 *yp = t0 36 Carnegie Mellon Simple Memory Addressing Modes Normal (R) Mem[Reg[R]] Register R specifies memory address Aha! Pointer dereferencing in C movq (%rcx),%rax

Displacement D(R) Mem[Reg[R]+D] Register R specifies start of memory region Constant displacement D specifies offset movq 8(%rbp),%rdx Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 37 Carnegie Mellon Complete Memory Addressing Modes Most General Form D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Rb: Ri: S: Constant displacement 1, 2, or 4 bytes Base register: Any of 16 integer registers Index register: Any, except for %rsp Scale: 1, 2, 4, or 8 (why these numbers?) Special Cases (Rb,Ri) Mem[Reg[Rb]+Reg[Ri]] D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D] (Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]

Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 38 Carnegie Carnegie Mellon Mellon Address Computation Examples %rdx 0xf000 %rcx 0x0100 Expression Address Computation Address 0x8(%rdx) 0xf000 + 0x8 0xf008 (%rdx,%rcx) 0xf000 + 0x100 0xf100 (%rdx,%rcx,4) 0xf000 + 4*0x100 0xf400 0x80(,%rdx,2)

2*0xf000 + 0x80 0x1e080 Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 39 Carnegie Mellon Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Arithmetic & logical operations Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 40 Carnegie Carnegie Mellon Mellon Address Computation Instruction leaq Src, Dst Src is address mode expression Set Dst to address denoted by expression Uses Computing addresses without a memory reference E.g., translation of p = &x[i]; Computing arithmetic expressions of the form x + k*y

k = 1, 2, 4, or 8 Example long long m12(long m12(long x) x) { { return return x*12; x*12; } } Converted to ASM by compiler: leaq leaq salq salq (%rdi,%rdi,2), (%rdi,%rdi,2), %rax %rax # # t t <<- x+x*2 x+x*2 $2, # $2, %rax %rax # return return t<<2 t<<2 Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 41

Carnegie Carnegie Mellon Mellon Some Arithmetic Operations Two Operand Instructions: FormatComputation addq Src,Dest Dest = Dest + Src subq Src,Dest Dest = Dest - Src imulq Src,Dest Dest = Dest * Src salq Src,Dest Dest = Dest << Src sarq Src,Dest Dest = Dest >> Src shrq Src,Dest Dest = Dest >> Src xorq Src,Dest Dest = Dest ^ Src andq Src,Dest Dest = Dest & Src orq Src,Dest Dest = Dest | Src Also called shlq Arithmetic Logical Watch out for argument order! No distinction between signed and unsigned int (why?) Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 42 Carnegie Carnegie Mellon Mellon Some Arithmetic Operations One Operand Instructions incq

decq negq notq Dest Dest Dest Dest Dest Dest Dest Dest = = = = Dest + 1 Dest 1 Dest ~Dest See book for more instructions Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 43 Carnegie Carnegie Mellon Mellon Arithmetic Expression Example long long arith arith (long (long x, x, long

long y, y, long long z) z) { { long long t1 t1 = = x+y; x+y; long long t2 t2 = = z+t1; z+t1; long long t3 t3 = = x+4; x+4; long long t4 t4 = = y y * * 48; 48; long long t5 t5 = = t3 t3 + + t4; t4; long long rval rval = = t2 t2 * * t5; t5; return

return rval; rval; } } arith: leaq addq leaq salq leaq imulq ret (%rdi,%rsi), %rax %rdx, %rax (%rsi,%rsi,2), %rdx $4, %rdx 4(%rdi,%rdx), %rcx %rcx, %rax Interesting Instructions leaq: address computation salq: shift imulq: multiplication Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition But, only used once 44 Carnegie Carnegie Mellon Mellon Understanding Arithmetic Expression Example arith: long long arith arith

(long (long x, x, long long y, y, long long z) z) { { long long t1 t1 = = x+y; x+y; long long t2 t2 = = z+t1; z+t1; long long t3 t3 = = x+4; x+4; long long t4 t4 = = y y * * 48; 48; long long t5 t5 = = t3 t3 + + t4; t4; long long rval rval = = t2 t2 *

* t5; t5; return return rval; rval; } } leaq addq leaq salq leaq imulq ret Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition (%rdi,%rsi), %rax %rdx, %rax (%rsi,%rsi,2), %rdx $4, %rdx 4(%rdi,%rdx), %rcx %rcx, %rax Register Use(s) %rdi Argument x %rsi Argument y %rdx Argument z %rax

t1, t2, rval %rdx t4 %rcx t5 # t1 # t2 # t4 # t5 # rval 45 Carnegie Mellon Machine Programming I: Summary History of Intel processors and architectures Evolutionary design leads to many quirks and artifacts C, assembly, machine code New forms of visible state: program counter, registers, ... Compiler must transform statements, expressions, procedures into low-level instruction sequences Assembly Basics: Registers, operands, move The x86-64 move instructions cover wide range of data movement forms Arithmetic C compiler will figure out different instruction combinations to

carry out computation Bryant and OHallaron, Computer Systems: A Programmers Perspective, Third Edition 46

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