CS 3501 - Chapter 4 Dr. Clincy Professor

CS 3501 - Chapter 4 Dr. Clincy Professor

CS 3501 - Chapter 4 Dr. Clincy Professor of CS Cover a section of Ch 4 Review both Exam 2 and Exam 3 Dr. Clincy Lecture Slide 1 Memory Organization We discussed a simple example of how memory is configured in Ch 3 we now will cover more detail of: How memory is laid out How memory is addressed Envision memory as a matrix of bits each row implemented as a register or storage cell and each row being the size of a addressable Word.

Each register or storage cell (typically called memory location) has a unique address. The memory addresses typically start at zero and progress upward Dr. Clincy Lecture 2 Memory Organization Computer memory consists of a linear array of addressable storage cells that are similar to registers. Memory can be byte-addressable, or word-addressable, where a word typically consists of two or more bytes. Byte-addressable case: although the Word could be multiple bytes, each individual byte would have an address with the lowest address being the address of the Word Memory is constructed of RAM chips, often referred to in terms of length width.

If the memory word size of the machine is 16 bits, then a 4M 16 RAM chip gives us 4 megabytes of 16-bit memory locations. Dr. Clincy Lecture 3 Memory Organization For alignment reasons, in reading 16-bit words on a byte-addressable machine, the address should be a multiple of 2 (i.e 2 bytes) For alignment reasons, in reading 32-bit words on a byte-addressable machine, the address should be a multiple of 4 (i.e 4 bytes) For alignment reasons, in reading 64-bit words on a byte-addressable machine, the address should be a multiple of 4 (i.e 8 bytes).

Dr. Clincy Lecture 4 Memory Organization How does the computer access a memory location corresponds to a particular address? Memory is referred to using notation: Length x Width (L x W) We observe that 4M can be expressed as 2 2 2 20 = 2 22 words means 4M long with each item 8 bits wide. Provided this is byte-addressable, the memory locations will be numbered 0 through 2 22 -1. Thus, the memory bus of this system requires at least 22 address lines. Dr. Clincy Lecture

5 Memory Organization Physical memory usually consists of more than one RAM chip. A single memory module causes all accesses to memory to be sequential - only one memory access can be performed at a time By splitting or spreading memory across multiple memory modules (or banks), access can be performed in parallel this is called Memory interleaving With low-order interleaving, the low order bits of the address specify which memory bank contains the address of interest. In high-order interleaving, the high order address bits specify the memory bank. Dr. Clincy Lecture 6

Memory Organization Example: Suppose we have a memory consisting of 16 2K x 8 bit chips. Memory is 32K = 25 210 = 215 15 bits are needed for each address. We need 4 bits to select the chip, and 11 bits for the offset into the chip that selects the byte. Dr. Clincy Lecture 7

Memory Organization In high-order interleaving the high-order 4 bits select the chip. In low-order interleaving the low-order 4 bits select the chip. Dr. Clincy Lecture 8 CS3501 Exam 2 & 3 Results Average E2 Score = 39 (Average Grade = 75) E2 Score SD = 22 (very large causes odd scale) Exam 2 Grading Scale:

96-74 A-grade (3 students) 73-51 B-grade (2 students) 50-28 C-grade (12 students) 27-5 D-grade (6 students) 4-0 F-grade (1 student) Average E3 Score = 46 (Average Grade = 75) E3 Score SD = 20 (very large) Exam 3 Grading Scale:

98-78 A-grade (2 students) 77-57 B-grade (5 students) 56-36 C-grade (10 students) 35-15 D-grade (6 students) 14-0 F-grade (1 student) In getting your grade logged, be sure and pass back the exam after we go over them Dr. Clincy 9

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