Decoder A Decoder 2-to-4, 3-to-8, n-to-2n S2 B

Decoder A Decoder 2-to-4, 3-to-8, n-to-2n S2 B

Decoder A Decoder 2-to-4, 3-to-8, n-to-2n S2 B S1 C S0 3:8 dec O0 O1 O2 O3 O4 O5 O6 O7 Enb ABC ABC ABC ABC

ABC ABC ABC ABC E A B C O0 O1 O2 O3 O4 O5 O6 O7 0 X X X 0 0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1

0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 1

1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 0

0 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0

0 0 1 2 Decoder 3 Design Using Decoder Applications: Implementing General Logic Any combinational circuit can be constructed using decoders and OR gates! Example: F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D' + A B C A F3 = (A' + B' + C' + D') B S3 S2 C S1 D S0 4:16 dec 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ABCD A BCD ABCD ABCD ABCD ABCD ABCD A BCD A BCD A BCD A BCD A BCD A B CD A B CD A B C D AB C D F1 F2 F3 Enb 4 Active Low

Decoder with Active Low Enable Active Low Outputs G A B Y0 Y1 Y2 Y3 1 X X 1 1 1 1 0 0 0 0 1 1 1 0

0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 5 74x139 dual 2-to-4 decoder

6 74x138 3-8 Decoder 7 74x138 3-8 Decoder 8 Using 3-State Buffers Can use 3-state buffers to share a single line for several devices. Decoder guarantees that no two buffers are on simultaneously. Some decoders have hi-Z outputs. 9 Decoders Can build a decoder by smaller decoders A A B S3 S2 C S1 D S0 4:16 dec

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B B S2 C S1 D S0 3:8 dec Enb O0 O1 O2 O3 O4 O5 O6 O7

C D B C S2 S1 D S0 3:8 dec Enb O0 O1 O2 O3 O4 O5 O6 O7 Enb 10 Decoders How to build a 5-32 decoder by using 4-16 and 2-4 decoders? 11 Decoders Decoder: a more general term Our focus was on binary decoders 12

7-Segment Decoder Seven-segment display: 7 LEDs (light emitting diodes), each one a controlled by an input 1 means on, 0 means off f b Display digit 3? g Set a, b, c, d, g to 1 e c Set e, f to 0 d 13 7-Segment Decoder C0 C5 C6 C4 C3 C1 C2 C C C C C C C 0 1 2 3 4 5 6 BCD-to-7-segment control signal decoder A B C D 14

7-Segment Decoder 7-Segment Decoder: Input is a 4-bit BCD code 4 inputs (A, B, C, D). Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed. a Example: Input: 0000BCD Output: 1111110 (a=b=c=d=e=f=1, g=0) f g e b c d 15 BCD-to-7Segment Truth Table Digit ABCD abcdefg Digit ABCD abcdefg 0 0000

1111110 8 1000 1 0001 0110000 9 1001 1111111 1110011 111X011 2 0010 1101101 1010 XXXXXXX 3 0011 1111001 1011 XXXXXXX 4 0100

0110011 1100 XXXXXXX 1101 XXXXXXX 5 0101 1011011 1110 XXXXXXX 6 0110 1011111 X011111 1111 XXXXXXX 7 0111 11100X0 1110000 ?? 16 K-maps

A AB 00 01 11 10 00 1 0 X 1 01 0 1 X 1 CD A AB 00 01 11 10

00 1 1 X 1 01 1 0 X 1 CD 1 1 X 1 X X 11 1 1 X X

10 1 0 11 10 00 1 0 X 1 01 0 1 X 0 X 1 0 X 00 01 11

10 00 1 0 X 1 01 0 0 X 0 CD 11 0 0 X 1 1 X X X 1

01 1 1 X 1 11 1 1 X X 10 0 1 X X B K-map for c A 00 01 11 10 00 1

1 X 1 01 0 1 X 1 CD 11 0 0 X 1 1 X X 00 01 11 10 00

0 1 X 1 01 0 1 X 1 11 1 0 X X 10 1 1 X X CD D X

C C 10 A AB D X C 10 X D X C 1 AB D 11 X A AB 01 1 K-map for b A

00 00 B K-map for a CD 10 C B AB 11 D C 1 01 D C 10 00 CD D 11 A AB 10

0 1 X X B B B B K-map for d K-map for e K-map for f K-map for g a = A + B D + C + B' D' b = A + C' D' + C D + B' c = A + B + C' + D d = B' D' + C D' + B C' D + B' C e = B' D' + C D f = A + C' D' + B D' + B C' g = A + C D' + B C' + B' C 17 Encoder Encoder Encoder: the inverse operation of a decoder. Has 2n input lines and n output lines. The output lines generate the binary equivalent of the input line whose value is 1. I0

I1 I2 I3 4-2 Binary Encoder z1 z2 19 Encoder A S2 B S1 C S0 O0 O1 O2 O3 3:8 decoder O4 O5 I0 I1 I2 I3 I4 I5 O6 O7

I6 I7 Z2 A Z1 8:3 encoder Z0 B C 20 Encoder Circuit Design Example: 8-3 Binary Encoder A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7 21 Encoder Circuit With Enable With Acknowledge 22 Application The number of inputs: large fewer lines 23 Encoder Design Issues Only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined

combination (for example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111. A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7 24 Priority Encoder Multiple asserted inputs are allowed; one has priority over all others. 25 K-Maps 26 Circuit 27 8-3 Priority Encoder 28 74x148 Features: inputs and outputs are active low. EI_L must be asserted for any of its outputs to be asserted. GS_L is asserted when the device is enabled and one or more of the request inputs is asserted. (Group Select or Got Something. ) EO_L is an enable output designed to be connected to the EI_L input of another 148 that

handles lower-priority requests. It is asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority 148 may be enabled. 29 74x148 Truth Table 30 Datasheets http://www.techlearner.com/C&D/index.htm http://users.otenet.gr/~athsam/database.htm Some sample datasheets in the course site. 32

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