Test Challenges for 3D Integrated Circuits ECE 7502

Test Challenges for 3D Integrated Circuits ECE 7502

Test Challenges for 3D Integrated Circuits ECE 7502 Class Discussion Reza Rahimi 10th Feb 2015 Rob ust ECE ow L 7502w Po S2015 er SI Customer Validate Requirements Verify Specification

Architecture PCB Architecture Logic / Circuits PCB Circuits Physical Design PCB Physical Design Fabrication PCB Fabrication Design and Test Development Verify

Test Manufacturing Test Packaging Test Rob ust Low Pow er SI PCB Test System Test Test Test Challenges

Lack of probe access for wafers Test access to modules in stacked wafers/dies Thermal concerns Design testability Test economics New defects arising from unique processing steps Wafer thinning Alignment Bonding Test-access and Test Scheduling Rob ust Low Pow er SI

3 How to build? Monolithic Require many changes in current process facilities [1] Die Stacking Can minimize the impact of altering existing manufacturing technology and equipment Not scalable. Limited to two layers Rob ust Low Pow er SI [1]

4 How to increase yield? Pretested Dies Sort the wafers first and stack matched dies Speed Power Obstacles Rob ust Low Pow er SI

Wafer probing Known good die New defect types Testing of the TSVs Thermal and Power-Delivery Considerations in Testing Test-access and Test Scheduling for Core-based SOCs Economics of Test and Its Relationship to Other Cost Factors: 5 Wafer probing Connection from the tester to the wafer Probing needles : Performance limit & cost contributor=>Lower frequency [www.wikipedia.org] Probe card applies a force of 3-10 g per probe =>60-120 kg Contactless Probe Rob ust

Low Pow er SI Solution: Scan chain and DFT 6 A contactless probe example[7] Rob ust Low Pow er SI 7 Wrapper cells TSV Cylindrical copper nails providing electrical connection from active front-side of a silicon

die through the silicon substrate to the back-side Prior to bonding, TSVs are not fully accessible because one of their ends is not connected to logic on other dies. The combinational part of die logic between the last level of scan cells and outbound TSVs cannot be observed, and that between inbound TSVs and first level of scan cells cannot be controlled. [3] Solution: Wrapper cell Rob ust Low Pow er SI 8 Design for Testability Tens of thousands TSVs Significant overhead. Higher latency.

Performance degradation. Problem: [3] Rob ust Low Pow er SI [3] [3] [3] 9 Contd Considering scan flops for more than one TSV Minimum number of wrappers Timing constraint on flops at the ends of critical paths

Finding globally optimum solution(Minimum wrapper cell count). NP-complete Heuristic algorithms. Rob ust Low Pow er SI 10 Converting to a graph problem [3] Rob ust Low Pow er SI

11 TSV fault models Left to Right: Rob ust Low Pow er SI Fault Free Full Open (insufficient TSV filling). Micro void (insufficient TSV filling). Oxide pin-hole (silicon side wall imperfection). [4]

12 BIST for TSV Defects[4] BIST Bock Solution: Localizing FF clock with control signal. Rob ust Low Pow er SI 13 Contd Can find d<0.99 Rob ust Low

Pow er SI [4] 14 Parametric Fault Model[6] Failure Analysis Understand the defect mechanism Parameters Rob ust Low Pow er

SI R_driver: on-resistance of the driving gate of the TSV R_TSV: lumped series resistance of the TSV C_TSV: lumped capacitance of the TSV L_TSV: inductance of the TSV R_leak: resistance of a leakage path away from the TSV 15 Parametric Fault Model[6] Ring Oscillator Testing delay faults XOR gates: to make the test structure symmetric Opposite values to the enable inputs of the two XORs Estimate the transition time by three steps Rob ust

Low Pow er SI First: both VOT inverters are in normal (oscillation period=T_ref) Second: TSV1s VOT inverter is switched to Schmitt-Trigger mode (oscillation period=T_ST1) Third:TSV2s VOT inverter is switched to Schmitt-Trigger mode (oscillation period=T_ST2) TSV1 delay has a linear relation with T_ST1-T_ref TSV2 delay has a linear relation with T_ST2-T_ref 16 Parametric Fault Model[6] Signature(T_ref,T_ST) Define fault boundary based on process variation model using Monte-Carlo simulation

Rob ust Low Pow er SI 17 Stacking[2] Sequential or rearranged? 3D test flows for rearranged stacking[2] Rob ust Low Pow er SI 18

Power and Thermal Issues[5] I/O pin limitation problem New Technology Lower VDD Lower noise margin Higher current per pin Higher IR and L(di/dt) noise 3D IC Rob ust Low Pow er SI Reduced footprint area Reduced interconnect wires Reduced the number of I/O pins too 19

Power and Thermal Issues[5] Stacked-VDD Balanced blocks Reduce current to 1/n of original value Noise and electro migration would be significantly alleviated Unbalanced blocks? Rob ust Low Pow er SI 20 Vdd Stacking Application in 3D-IC Allocate a single Vdd value to each tier of the 3D IC. high-current blocks will be stacked up over each other Thermal issues Algorithm

Rob ust Low Pow er SI Divide each tier to regions based on Regulators location Euclidean distance or any other metric. Assign a Vdd level to each module. Split down modules to sub-modules. Assign sub-modules in different regions but with same Vdd Use a low pass filter for I(t) 21

Contt[5] Rob ust Low Pow er SI 22 Discussion questions Rob ust Low Pow er SI 1. How does the contact-less probes work? 2. How can DFT help probing problem? 3. How can DFT help in finding Known Good

Dies? 4. How BIST can help us in finding defects in TSVs? 5. How can we solve 3D-ICs thermal problem using VDD shifting? 23 Papers Rob t s u

Low Pow er SI [1] Lee, H; Chakrabarty, K, "Test Challenges for 3D Integrated Circuits," Design & Test, IEEE , vol.PP, no.99, pp.1,1, 0 doi: 10.1109/MDT.2009.102 [2] Chang Hao; Liang Huaguo; Li Yang; Ouyang Yiming, "Optimized stacking order for 3Dstacked ICs considering the probability and cost of failed bonding," VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on , vol., no., pp.1,4, 2830 April 2014 [3] Agrawal, M.; Chakrabarty, K., "A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs," Test Conference (ITC), 2013 IEEE International , vol., no., pp.1,10, 6-13 Sept. 2013 [4] Di Natale, G.; Flottes, M.-L.; Rouzeyre, B.; Zimouche, H., "Built-in self-test for manufacturing TSV defects before bonding," VLSI Test Symposium (VTS), 2014 IEEE 32nd , vol., no., pp.1,6, 13-17 April 2014 [5] Y. Zhan and S. Sapatnekar. Automated module assignment in stacked-vdd designs for high-efficiency power delivery. ACM Journal on Emerging Technologies in Computing Systems, 4(4), 2008 [6] Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Sunter, S., "A unified method for parametric fault characterization of post-bond TSVs," Test Conference (ITC), 2012 IEEE International , vol., no., pp.1,10, 5-8 Nov. 2012 24

Paper Map (e.g.) [4] TSv Fault [5] stack vdd Assigning blocks to different vdd [3] Wrapper cell [2] stack reordering Rob ust Low Pow er SI Increase Yield A DFT method for 3D IC A Parametric BIST method for

3D IC [4] TSV Fault A BIST method for 3D IC [1] A survey on 3D IC Test 25 Glossary Rob ust Low Pow er SI 26

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