Research Topics - cseweb.ucsd.edu

Research Topics - cseweb.ucsd.edu

ROAD: Routability Analysis & Diagnosis Based on SAT Techniques SLIP 2018 (Published) ISPD 2019 (Accepted) CK Cheng CSE Department UC San Diego 1 PHYSICAL DESIGN GETTING HARDER Keep Scaling Technologies Design Rule Complexity Rising More and more complex of Place & Routing in Physical Design !! 2/47 INTRODUCTION: DESIGN PROCEDURE OF PHYSICAL DESIGN Efforts to improve pin accessibility Failure to produce routable (or routed) design in each step loop-back of PD procedure undesired additional design cost BEOL-aware cell layout design Gate Netlist routing-driven placement Migration, congestion Placement by (1) or (2) Yes Routing ECO (Engineering Change Order) No IF Unroutable Routable? New detailed routing algorithm pin-access planning DRC violations

manufacturability Routed Layout 3/47 INTRODUCTION : DESIGN RULES Performance Design Rule Interconnect parasites Electronic migration Geometry Design Rules Minimum area rule End of line spacing rule: minimal distance between two ends of wire segments Via rules: minimal spacing between two vias, and stacked via rule. Design Processes to mitigate ProcessDesign Gap LELE (litho-etch-litho-etch) SADP (self-aligned double patterning) SAQP (self-aligned quadruple patterning) 4/47 INTRODUCTION : NEXT GEN LITHO. (EUV) Resource Requirement Utility Electrical power (kW) Cooling water flow (L/min) Gas lines https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography 90 W output ArF immersion double patterning 200 W output EUV 532 1600 6 49 75 3 5/47 DESIGN RULE-CORRECT ROUTABILITY ANALYSIS ILP: Optimal but 1048s (~18min) !

Gate Netlist Placement Given Pin-Layout SAT : Not Optimized but 2s !!!!! Power Rail Pin 16 15 14 11 4 6 2 19 8 9 17 21 23 22 20 Routable? SAT Method Quick go/no-go Decision 18 Pin 12 13 0 Via3-4 M1-2 1 M2-3 5 3 M3-4

7 10 6/47 WHAT IS SAT (BOOLEAN SATISFIABILITY) ? SAT (Boolean Satisfiability) Find an assignment so that the formula is true (1) (Satisfiable) , or prove that no such assignment exists (0) (Unsatisfiable) 1, 1, 1() ( ) ( ) Usually, Product of Sum (i.e. CNF) is normal representation for SAT formula Truth Table X Y F(x,y) 0 0 1 0 1 0 1 0 0 1 1 1 Product of Sum (CNF)

Sum of Product (DNF) ( ) ( ) ( ) ( ) Equivalent Representations 7/47 SAT-BASED FRAMEWORK FOR ROUTABILITY ANALYSIS ILP-based routability optimization SAT-based routability analysis Fast and Precise Routability Analysis wit Our Proposed Framework Routability Analysis Flow Logic Simplification ILP Patterns per ILP Formula Testcase (i.e., Switchbox) Generation SAT-Friendly ILP Formulation Logic Minimizer ILP-to-SAT Conversion Espresso [26] Solvers Results of Routability Analysis ILP Solver SAT Solver CPLEX [27] plingeling [28] by ILP

[27] IBM ILOG CPLEX, http://www.ilog.com/products/cplex/. [28] plingeling, Multi-Threading SAT Solver, http://fmv.jku.at/lingeling/. by SAT Inputs - #Vertical and Horizontal Tracks - Pin Density - Switchboxes 3D Routing Graph Source-Sink Definition ILP Inputfiles SAT Inputfiles Reduced SAT Inputfiles ILP Result: Routing Feasibility, Wirelength, Metal Cost, etc. SAT Result: Routing Feasibility, SAT Solution if Satisfiable 8/47 NEXT STEP : ROUTABILITY DIAGNOSIS AND ESTIMATION Conflict Diagnosis in Unroutable Case using SAT Technique Exact Location of Conflict Fast Trouble-shooting for Designer Exact Conflict Relation Guideline for Design Rule Manager Routability Quantification Estimate the routing possibility upon given switch-box go/no-go decision for revision of switch-boxgo/no-go decision for revision of switch-box 9/47 RODE : ROUTABILITY DIAGNOSIS & ESTIMATION Routability Analysis Using SAT Formulation Estimation Diagnosis

Unroutable Layout Node : U (variable) MUS MUS Extraction (Minimal Unsatisfiable Subset) Clause Minimization Initial Propagation Ub Edge : D (clause) (Geometric Information of Switch-Box) Conflict Region Decision (DLS) Us (Decision with Longest-Path Search) Propagation (PTA/PFA) BCP Iteration PIG Up (Propagation with True/False Assignment) No Conflict? Yes Conflict Information (Conflict Geometry / Design Rule) DAG : H(U,D) 10/47 RODE : NOTATION & PIN-LAYOUT CONFIGURATION

M1 in G M2 in G 2 1 2 1 2 1 2 2 M3 in G 1 PIN #1 V-Track Power Rail Grid M4 in G H-Track Outer-Pin Connection 11/47 PROPOSED SAT FORMULATION DIAGRAM The Multi-commodity network flow formulation (F) Conditional Design Rule (D) () Commodity Flow Conservation (CFC) Exclusiveness

Use of Vertex (EUV) ( , ) Conditional Design Rules (D) 1. End-of-Line Space Rule (EOL) 2. Minimum Area Rule (MAR) 3. Via Rule (VR) , Edge Assignment (EA) Metal Segment (MS) , Geometry Variable (GV) , Flow Formulation (F) 12/47 SAT FORMULATION FLOW FORMULATION (F) Commodity Flow Conservation (CFC) Vertex is not a source or sink 1) Only one incoming/outgoing pair is allowable for all commodities. 2) This commodity dont use this vertex.

Vertex is a source or sink Exactly-One (EO) Constraint 13/47 SAT FORMULATION FLOW FORMULATION (F) Exclusiveness Use of Vertex (EUV) Vertex is not a source or sink 1) Only n net flow can be assigned if a certain edge is occupied by the n net 2) This net dont use this vertex.

Vertex is a source or sink At-Most-One (AMO) Net Constraint 14/47 SAT FORMULATION FLOW FORMULATION (F) Edge Assignment (EA) ( , ) , Logical Imply. : edge is used by n net if m commodity of n net use this edge It requires for multi-commodity flow Metal Segment (and Exclusiveness Use of Edge) (MS) AMO Constraint 15/47

SAT FORMULATION DESIGN RULE FORMULATION (D) Geometric Variable (GV) End-of-Line indicator of each vertex for geometric conditional design rule. ,( , 2) =1 ( , 2) ,(1, ) =1 ,(2, ) =1 (0, ) (1, ) (2, ) ( , 3) ,( ,1) =1 ( ,1) 16/47 SAT FORMULATION DESIGN RULE FORMULATION (D) Minimum Area Rule (MAR) A metal segment must cover at least three vertices (AMO) , + , + , + , 1, True Table Karnaugh Map CNF conversion by Espresso (Logic Minimizer) Violation , = , =1 , = , =0 No Violation , =1 , = , = , =0

17/47 SAT FORMULATION DESIGN RULE FORMULATION (D) End-of-Line (EOL) Space Rule The minimum distance between tips must be larger than 2 Manhattan distance (AMO) Violation Violation No Violation 18/47 SAT FORMULATION DESIGN RULE FORMULATION (D) Via Rule (VR) The distance between two vias should be larger sqrt(2) Euclidean Distance (AMO) + 2

+ 2 +1 Violation +1 No Violation 19/47 SAT FORMULATION DESIGN RULES ARE ALWAYS MIXED Mixed Design Rule Violation

1 2 VIA(M1M2) (a) Violation (VR OK, EOL Fail) 1 2 (b) Violation (VR OK, EOL Fail) VIA(M2M3) No Violation Violation No Violation No Violation 20/47 DESIGN RULE-CORRECT ROUTABILITY ANALYSIS Flow Feasibility (F) Conjunction of each subsets Design Rule Formulation (D) Design Rule-correct Routability ( R ) L : Layout Structure Map the geometry information of the switch box 21/47 (1) MINIMAL UNSATISFIABLE SUBSET (MUS) 22/47 (2) BOOLEAN CONSTRAINT PROPAGATION (BCP)

BCP The procedure is based on Unit Clauses If a set of clauses contains the unit clause , the other clauses are simplified by the application of the two following rules Every clause containing is removed In every clause that contains this literal is deleted * BCP Iteration Example Clause set: https://en.wikipedia.org/wiki/Unit_propagation 23/47 (3) PARTIAL IMPLICATION GRAPH (PIG) PIG in Our Framework Directed Acyclic Graph which Nodes are Variables, Edges are Clauses. The implication relation between variable assignment from constraint clause PIG of the propagation Clause set: a c d https://en.wikipedia.org/wiki/Unit_propagation 24/47 AFTER INITIAL PROPAGATION The intersection range between GV and MS Estimated Conflict Range Power Rail 0 1 2 7 9 12 4 3

1 #V_Tracks= 9 #H_Tracks= 13 PinDensity= 100% 2 3 4 14 Pins: 0-13 8 Outer Pins: 14-21 5 6 10 Nets: {1 7 18}, {2 6 20}, {3 10}, {13 19}, {9 12}, {4 17}, {8 14}, {0 16}, {5, 15}, {11 21} 7 8 9 10 11 12 0 10 13 8 11 5 6 0 1 6 7 2 3 4 5 Estimated Conflict Region

8 25/47 DLS (DECISION WITH LONGEST-PATH SEARCH) Longest-path search is most comprehensive explanation about failure Via Position / Direction of Element are determined at DLS phase Blocked via (M1 M2) 0 1 2 7 9 12 4 Selected ! 1 3 2 7 9 12 4 3 1 2 7 9 12 4 3 1 2 3 4

5 6 Conflict @ 2nd 7 Conflict @ 4th Conflict @ 1st 8 9 10 11 10 13 8 11 5 12 0 1 2 3 4 5 6 0 6 7 10 13 8 11 5 6 0 10 13 8 11 5 6 0

8 26/47 PTA (PROPAGATION WITH TRUE ASSIGNMENT) BCP propagation with True Assignment (Us) (3) (2) 2 (1) 1 (2) ( 1 2 ) 1 (3) 2 (1) 27/47 PTA (PROPAGATION WITH TRUE ASSIGNMENT) PTA Result of #1 VIA @ 9_13_100 0 1 2 7 9 12 4 3 1 2 3 4

5 6 7 ( 3,10,1) ,(3,10,2 )=1 (4,9,1)(4,9,2) =0 (4,10,1)(4,10,2) =0 (3,10,2 )(3,10,3)=0 8 9 10 11 10 13 12 0 1 2 8 3 11 4 5 5 6 6 Blocked via (M1 M2) Blocked via (M2 M3) 0 7 9 ( 4,9,1 ) ,(4,9,2)

=0 8 9 ( 4,10,1 ) ,(4,10,2) 6 =0 (3,10,2 ) ,(3,10,3) =0 6 (4,9,1)(4,9,2)=0 0 (3,10,2)(3,10,3)=0 90 (4,10,1)(4,10,2)=0 9 0 Assigned via (M1 M2) 28/47 PFA (PROPAGATION WITH FALSE ASSIGNMENT) BCP propagation with False Assignment (Us) Via-to-via spacing / Stacked Via / Vias in same pin / element with direction against PTA + 2 + 2 +1

2 1 +1 2 1 Blocked via Blocked in-layer element 29/47 PFA (PROPAGATION WITH FALSE ASSIGNMENT) PFA Result of #1 VIA @ 9_13_100 0 1 2 7 9 12

4 3 1 2 3 4 5 6 7 9 0 (11)(4,10,1)=0 90 (4,9,1)(4,10,1)=0 (11)(4,9,1)=0 9 90 (11)(4,8,1)=1 0 (4,8,1)(4,9,1)=0 9 (4,8,1 ) ,(4,8,2)=1 90 (4,8,1)(4,8,2)=1 9(4,8,2 ) ,(4,8,3) =0 (4,8,1)(4,8,2) =1 (4,8,2)(4,8,3)=0 9 0 90 (4,8,2)(4,8,3)=0 8 ( 3,10,2) ,(4,10,2 )=0 9 10

11 12 0 10 13 8 11 5 6 0 1 6 7 2 3 4 5 Blocked via (M1 M2) Blocked via (M2 M3) Assigned via (M1 M2) Blocked in-layer element ,(3,10,2 )=1 6(3,10,2 ) ,(4,10,2) =0 8 6 0 (3,10,2)(4,10,2)=0 ,(4,10,2) =0 (4,10,2)(5,10,2)=0 ,(5,10,2 )=0 8 =0

8(4,10,2 ) ,(5,10,2) =0 (5,10,2 )(6,10,2 )=0 80 (4,10,2)(5,10,2)=0 ( 5,10,2 ) ,(6,10,2) 9 0 (4,10,1)(4,10,2)=0 30/47 DIAGNOSIS RESULT OF 9_13_100 4th via @ PFA phase Conflict encounter ! Blocked via (M1 M2) 0 1 2 7 9 12 4 3 70 ( 0)(7,8,1)=0 70 ( 0)(7,9,1)=0 1 2 3 4 5

70 ( 0)(7,10,1)=1 70 ( 0)(7,10,1)=0 6 7 8 9 10 CONFLICT Information 11 12 0 10 13 8 11 5 6 0 1 6 7 2 3 4 5 Geometry : (Pin0) (7,10,1) Design Rule : CFC VR Rule 8 31/47 ROUTABILITY ESTIMATION USING PRACTICAL PIN-LAYOUT Routability Estimation using Automated Generated Pin-layout Rents Rule Practical Pin-layout Routability Quantification Useful Information to Designer

With One Row of Pins With Two Row of Pins 32/47 ROUTABILITY ESTIMATION UNROUTABILITY TREND U n ro u ta b ility (a vg .) Unroutability Comparison vs. the number of pin row 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 50 60 70 80 90 100 avg. The Number of Grid 33/47 ROUTABILITY DIAGNOSIS ROOT CAUSES The Root causes of routing failure Conflict Pin-shape (CP) : Pin-Accessibility Problem! Simple-CP : Intrinsic Pattern in given Pin-layout Propagated-CP : Simple-CP appears after some propagations Routing Congestion The lack of routing resources such as #Track and #Layer 34/47 UNROUTABLE LAYOUT CLASSIFICATION SIMPLE-CP

Simple-CP with 3-3-n-3-3 pattern 1 2 7 9 12 4 3 #V_Tracks= 9 , #H_Tracks= 13 PinDensity= 100% 14 Pins: 0-13 8 Outer Pins: 14-21 10 Nets: {1 7 18}, {2 6 20}, {3 10}, {13 19}, {9 12}, {4 17}, {8 14}, {0 16}, {5, 15}, {11 21} Unroutable Pin-shape Pattern 33n33 10 13 8 11 5 6 0 35/47 UNROUTABLE LAYOUT CLASSIFICATION PROPAGATEDCP Propagated-CP : Main Concern of Pin-accessibility Why designer dont change Pin-shape? 13 11 5 7 4 3 0

13 11 5 1 8 7 4 3 1 2 3 4 5 6 7 8 9 10 11 1 8 6 2 0 10 12 9 #V_Tracks= 12, #H_Tracks= 13 PinDensity= 70% 14 Pins: 0-13 9 Outer Pins: 14-22 10 Nets: {2 13 14}, {10 12 15}, {4 8 21}, {0 22}, {6 20}, {3 16}, {7 17}, {5 11}, {9 19}, {1 18}

12 0 1 2 3 6 4 2 5 0 10 12 9 6 7 8 9 10 11 Unroutable Pin-shape Pattern 333 36/47 UNROUTABLE LAYOUT CLASSIFICATION ROUTING CONGESTION Routing Congestion : Technology Limitation Identification! ` 5 11 1 6 10 3 2 8 9

0 7 4 #V_Tracks= 15, #H_Tracks= 7, PinDensity= 90% 12 Pins: 0-11 8 Outer Pins: 12-19 9 Nets: {2 11 14}, {5 8 13}, {3 15}, {6 12}, {9 16}, {1 4}, {7 19}, {0 17}, {10 18} All tracks are occupied / blocked !! (a) 0 ` 5 11 1 6 10 3 2 8 9 0 7 4 0 ` 1 2 5 11 3 4 5

6 7 8 9 1 6 10 3 2 8 1 0 9 11 0 1 2 7 1 3 4 1 4 1 2 3 4 5 6 37/47 ROUTABILITY DIAGNOSIS EXPERIMENTAL STATISTICS Total Diagnosis Time MUS Extraction Time + Decision & Propagation Time

Diagnosis Performance (Complexity and Execution Time) depends on the root causes of routing failure CP Pattern Case is less than 30 seconds to get the result. Routing Congestion Case is relatively hard to find the failure causes. 38/47 ROUTABILITY DIAGNOSIS ROOT CAUSE CONFIGURATION Same Grid Number with different number of pins row 39/47 PUBLICATIONS WITH THIS PROJECT 1. Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng. Fast and Precise Routability Analysis with Conditional Design Rules. SLIP 2018 2. Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bil Lin and Chung-Kuan Cheng. RODE: Efficient Routability Diagnosis and Estimation Framework Based on SAT Techniques. ISPD 2019 (Will Published at 2019/April) 3. Journal Extension will be prepared soon. 40/47 SAT Solving Performance Improvement 41 CSP TO SAT Converting Encoding Method Direct Encoding (Sparse Encoding) Ordering Encoding Log Encoding CSP (Constraint Satisfaction Problem) Constraint Optimization Constraint Simplification ABC (AIGs) MIG Techniques SAT (Boolean Satisfiability) CNF Optimization Preprocessing (BCP) Encoding Techniques for EO / AMO SAT Encodings of Finite CSPs

42/47 ROAD IMPROVEMENT (1) SUPER OUTER NODE (SON) Super Outer Node : Representation Simplifying Conventional Super Node Super Outer Node (SON) 43/47 ROAD IMPROVEMENT (2) ENCODING TECHNIQUES FOR AMO/EO Commodity Flow Conservation (CFC) Exclusiveness Use of Vertex (EUV) 1. End-of-Line Space Rule (EOL) 2. Minimum Area Rule (MAR) Conditional Design Rules 3. Via Rule (VR) Edge Assignment (EA) Metal Segment (MS) Layout Structure Map Type Formulation CFC (Commodity Flow Conservation) Flow Design Rule

EUV (Exclusiveness Use of Vertex) Geometry Variable (GV) CSP Side (Constraints) (Case I) EO (Exactly-one) (Case II) Neither(0) or Flow(2) (Case I) AMO (At-Most-One) Net SAT Side (CNF Representation) Bimander or Commander AMO Net Variable (Commander Encoding) Bimander or Commander AMO (Case II) Neither (0) or Flow (2) MIG Technique can be a candidate - EA (Edge Assignment) Logically Imply - MS (Metal Segment) AMO Net GV (Geometric Variable) See the variable hierarchy MAR (Minimum Area Rule) AMO Pairwise AMO (Only 4 variables) EOL (End-of-Line Rule) AMO Pairwise AMO (Only 3 variables)

VR (Via Rule) AMO Pairwise AMO (Only 4 variables) Metal Variable (Commander Encoding) Bimander or Commander AMO - 44/47 ROAD IMPROVEMENT (3) PREPROCESSING : BCP BCP The procedure is based on Unit Clauses If a set of clauses contains the unit clause , the other clauses are simplified by the application of the two following rules Every clause containing is removed In every clause that contains this literal is deleted * BCP Iteration Example Clause set: 45/47 SIMPLIFIED SAT FORMULATION In Largest Case (20x19 x 90% Density) of SLIP 2018 29.4% of #Variable / 0.9% of #Literal / 0.7% of #Clause are acquired using simplification techniques ( SON , Commander Encoding for AMO/EO , BCP Preprocessing ) #Net = Number of Net , #Pin = Number of Pin, #OTP = Number of outer directional pin SLIP 2018 IDX #VT #HT Density #Net #Pin #OTP #Var (Reduced) 01 05 06 07 08 20

20 20 20 20 19 19 19 19 19 60 60 60 60 60 01 02 05 06 07 20 20 20 20 20 19 19 19 19 19 70 70 70 70 70 02 04 07 08 09 20 20 20 20

20 19 19 19 19 19 80 80 80 80 80 01 02 03 04 05 20 20 20 20 20 19 19 19 19 19 90 90 90 90 90 13 12 11 17 11 12.8 2.0 12 17 22 13 9 14.6

4.1 12 18 10 13 16 13.8 2.6 13 16 14 16 18 15.4 1.6 431,012 400,298 371,875 562,552 373,618 427,871.0 64,534.3 456,388 630,778 825,198 488,864 359,387 552,123.0 147,800.9 499,984 723,379 432,168 534,104 648,089 567,544.8 95,552.2 592,616 709,314 628,480 711,502 799,279 688,238.2 65,866.2 20 20 19 21 18 19.6

0.9 21 23 27 22 22 23.0 1.9 24 28 23 25 25 25.0 1.5 27 30 29 29 28 28.6 0.9 45 44 43 49 43 44.8 2.0 50 55 60 51 47 52.6 4.1 55 61 53 56 59 56.8 2.6 62 65 63 65 67 64.4 1.6

SON / Commander Encoding / BCP #Cla #Lit (Reduced) (Reduced) RA Runtime #Var(Cmd) Ratio (s) 96,473,257 48,337,366 UR 85,526,509 42,952,726 R 68,799,905 34,618,703 R 162,026,012 80,580,373 R 62,627,649 31,494,496 R 95,090,666.4 47,596,732.8 32,451,956.3 16,009,097.1 94,972,296 47,453,133 UR 193,827,142 96,163,509 UR 406,276,249 201,309,416 UR 116,477,593 58,134,373 UR 69,318,982 34,868,818 UR 176,174,452.4 87,585,849.8 111,679,639.3 55,172,057.6 122,322,363 61,035,488 UR 309,764,276 153,877,808 UR 87,443,954 43,751,284 UR 148,568,883 74,077,401 UR 206,410,613 102,454,952 UR 174,902,017.8 87,039,386.6 71,048,794.6 35,173,593.0 173,294,545 86,233,255 UR 292,560,379 145,452,322 UR 221,727,502 110,385,191 UR 274,654,058 136,427,298 UR 312,811,632 154,873,505 UR 255,009,623.2 126,674,314.2 46,407,773.9 22,890,112.3 16.3 26.7 23.3 34.7 23.1 24.8 5.5 18.5 31.2 65.0 20.0 22.8

31.5 15.8 20.1 52.1 15.4 24.8 33.3 29.1 11.8 30.8 46.6 35.8 45.9 53.5 42.5 7.4 135,466 134,180 130,346 147,827 124,157 134,395.2 7104.3 147,724 162,341 187,506 153,988 145,553 159,422.4 13880.2 165,445 192,649 157,099 169,686 177,015 172,378.8 10963.4 190,508 205,863 196,980 203,689 206,759 200,759.8 5627.3 31.4% 33.5% 35.1% 26.3% 33.2%

31.9% 2.8% 32.4% 25.7% 22.7% 31.5% 40.5% 30.6% 5.6% 33.1% 26.6% 36.4% 31.8% 27.3% 31.0% 3.3% 32.1% 29.0% 31.3% 28.6% 25.9% 29.4% 2.0% #Lit (Cmd) Ratio Runtime #Cla (Cmd) Ratio RA Runtime (s) Ratio 1,419,964 1,396,454 1,349,182 1,585,704 1,333,662 1,416,993.2 82093.9 1,567,126 1,761,441 2,025,787 1,633,257 1,487,337 1,694,989.6 171815.0 1,756,142 2,043,491 1,655,984 1,793,676

1,919,439 1,833,746.4 122857.3 2,041,136 2,183,917 2,079,723 2,191,987 2,267,125 2,152,777.6 74591.3 1.5% 1.6% 2.0% 1.0% 2.1% 1.6% 0.4% 1.7% 0.9% 0.5% 1.4% 2.1% 1.3% 0.5% 1.4% 0.7% 1.9% 1.2% 0.9% 1.2% 0.4% 1.2% 0.7% 0.9% 0.8% 0.7% 0.9% 0.2% 544,926 536,749 518,995 604,959 512,711 543,668.0 29925.3 599,056 669,522 772,246 623,586

572,780 647,438.0 63963.9 671,021 782,020 633,237 685,908 729,677 700,372.6 46731.5 778,831 835,296 796,664 835,778 860,436 821,401.0 26918.5 1.1% 1.2% 1.5% 0.8% 1.6% 1.3% 0.3% 1.3% 0.7% 0.4% 1.1% 1.6% 1.0% 0.4% 1.1% 0.5% 1.4% 0.9% 0.7% 0.9% 0.3% 0.9% 0.6% 0.7% 0.6% 0.6% 0.7% 0.1% UR R R R

R UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR 2.2 13.8 13.4 9.0 15.8 10.8 4.4 1.1 1.2 6.2 2.7 9.7 4.2 3.0 1.5 1.5 1.2 1.3 2.4 1.6 0.4 1.7 1.5 1.6 1.9 1.7 1.7 0.1 13.5% 51.7%

57.5% 25.9% 68.4% 43.4% 18.7% 5.9% 3.8% 9.5% 13.7% 42.5% 15.1% 12.9% 7.5% 2.9% 7.8% 5.2% 7.2% 6.1% 1.7% 5.5% 3.2% 4.5% 4.1% 3.2% 4.1% 0.8% 46/47 MORE FUTURE WORK Utilizing Framework Photonic Interconnection Design based on Waveguide technology Utilizing Diagnosis : Pin-shape Pattern Conflict Machine Learning can be applicable by Pattern Training Placement Refinement Technique Suggestion Utilizing Diagnosis : Routing Resource Conflict Case Identifying Technology Limitation Pin-Shape Design (Pin also the variable, not given) Optimized SAT Solution using SMT Technique Minimum Wire/Metal Cost based on SAT 47/47 APPENDIX 48/47 M1 ROUTING DIFFICULTY

Cell Design Using M1 (Currently, Bi-Directional) 49/47

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