Data-Level Parallelism in Vector, SIMD, and GPU Architectures Copyright 2012, Elsevier Inc. All rights reserved. 1 Single instruction stream, single data stream (SISD) Single instruction stream, multiple data streams (SIMD) Multiple instruction streams, single data stream (MISD) Vector architectures Multimedia extensions Graphics processor units
Classes of Computers Flynns Taxonomy No commercial implementation Multiple instruction streams, multiple data streams (MIMD) Tightly-coupled MIMD Loosely-coupled MIMD Copyright 2012, Elsevier Inc. All rights reserved. 2 SIMD architectures can exploit significant datalevel parallelism for: matrix-oriented scientific computing media-oriented image and sound processors SIMD is more energy efficient than MIMD
Introduction Introduction Only needs to fetch one instruction per data operation Makes SIMD attractive for personal mobile devices SIMD allows programmer to continue to think sequentially Copyright 2012, Elsevier Inc. All rights reserved. 3 Vector architectures SIMD extensions Graphics Processor Units (GPUs) Introduction
SIMD Parallelism For x86 processors: Expect two additional cores per chip per year SIMD width to double every four years Potential speedup from SIMD to be twice that from MIMD! Copyright 2012, Elsevier Inc. All rights reserved. 4 Figure 4.1 Potential speedup via parallelism from MIMD, SIMD, and both MIMD and SIMD over time for x86 computers. This figure assumes that two cores per chip for MIMD will be added every two years and the number of operations for SIMD will double every four years. Copyright 2011, Elsevier Inc. All rights Reserved. 5 Basic idea:
Read sets of data elements into vector registers Operate on those registers Disperse the results back into memory Vector Architectures Vector Architectures Registers are controlled by compiler Used to hide memory latency Leverage memory bandwidth Copyright 2012, Elsevier Inc. All rights reserved. 6 Vector Supercomputers
Epitomized by Cray-1, 1976: Scalar Unit + Vector Extensions Load/Store Architecture Vector Registers Vector Instructions Hardwired Control Highly Pipelined Functional Units Interleaved Memory System No Data Caches No Virtual Memory Copyright 2012, Elsevier Inc. All rights reserved. 7 Cray-1 (1976) Copyright 2012, Elsevier Inc. All rights reserved. 8 Cray-1 (1976)
Copyright 2012, Elsevier Inc. All rights reserved. 9 Example architecture: VMIPS Loosely based on Cray-1 Vector registers Fully pipelined Data and control hazards are detected Vector load-store unit Each register holds a 64-element, 64 bits/element vector
Register file has 16 read ports and 8 write ports Vector functional units Vector Architectures VMIPS Fully pipelined One word per clock cycle after initial latency Scalar registers 32 general-purpose registers 32 floating-point registers Copyright 2012, Elsevier Inc. All rights reserved. 10 Figure 4.2 The basic structure of a vector architecture, VMIPS. This processor has a scalar architecture just like MIPS. There are also eight 64-element vector registers, and all the functional units are vector functional units. This chapter defines special vector instructions for both arithmetic and memory accesses. The figure shows vector units for logical and integer operations so that VMIPS looks like a standard vector processor that usually includes these units; however, we will not be discussing these units. The vector and scalar registers have a significant number of read and write ports to allow multiple simultaneous vector operations. A set of
crossbar switches (thick gray lines) connects these ports to the inputs and outputs of the vector functional units. Copyright 2011, Elsevier Inc. All rights Reserved. 11 Vector Programming Model Copyright 2011, Elsevier Inc. All rights Reserved. 12 ADDVV.D: add two vectors ADDVS.D: add vector to a scalar LV/SV: vector load and vector store from address Vector Architectures VMIPS Instructions Example: DAXPY (double precision a*X+Y)
L.D F0,a ; load scalar a LV V1,Rx ; load vector X MULVS.D V2,V1,F0 ; vector-scalar multiply LV V3,Ry ; load vector Y ADDVV V4,V2,V3 ; add SV Ry,V4 ; store the result Requires 6 instructions Copyright 2012, Elsevier Inc. All rights reserved. 13 Example: DAXPY (double precision a*X+Y) L.D F0,a ; load scalar a DADDIU R4,Rx,#512 ; last address to load Loop: L.D F2,0(Rx) ; load X[i]
MUL.D F2,F2,F0 ; a x X[i] L.D F4,0(Ry) ; load Y[i] ADD.D F4,F2,F2 ; a x X[i] + Y[i] S.D F4,9(Ry) ; store into Y[i] DADDIU Rx,Rx,#8 ; increment index to X DADDIU Ry,Ry,#8 ; increment index to Y SUBBU R20,R4,Rx ; compute bound BNEZ R20,Loop ; check if done Vector Architectures DAXPY in MIPS Instructions Requires almost 600 MIPS ops Copyright 2012, Elsevier Inc. All rights reserved. 14
Vector Instruction Set Advantages Copyright 2012, Elsevier Inc. All rights reserved. 15 Vector Arithmetic Execution Copyright 2012, Elsevier Inc. All rights reserved. 16 Vector Memory System Cray-1, 16 banks, 4 cycle bank busy time, 12 cycle latency Bank busy time: Cycles between accesses to same bank Base Stride Vector Registers Address Generator + 0 1 2 3 4 5 6 7 8 9 A B C D E F Memory Banks 02/29/2020
17 Execution time depends on three factors: VMIPS functional units consume one element per clock cycle Length of operand vectors Structural hazards Data dependencies Vector Architectures Vector Execution Time Execution time is approximately the vector length Convoy
Set of vector instructions that could potentially execute together Copyright 2012, Elsevier Inc. All rights reserved. 18 Sequences with read-after-write dependency hazards can be in the same convoy via chaining Chaining Vector Architectures Chimes Allows a vector operation to start as soon as the individual elements of its vector source operand become available Chime
Unit of time to execute one convoy m convoys executes in m chimes For vector length of n, requires m x n clock cycles Copyright 2012, Elsevier Inc. All rights reserved. 19 Vector Instruction Execution ADDV C,A,B Execution using one pipelined functional unit A[6] A[5] A[4] A[3] 02/29/2020 B[6] B[5] B[4] B[3] Execution using four
pipelined functional units A[24] A[20] A[16] A[12] B[24] B[20] B[16] B[12] A[25] A[21] A[17] A[13] B[25] B[21] B[17] B[13] A[26] A[22] A[18] A[14] B[26] B[22]
B[18] B[14] A[27] A[23] A[19] A[15] B[27] B[23] B[19] B[15] C[2] C[8] C[9] C[10] C[11] C[1] C[4] C[5]
C[6] C[7] C[0] C[0] C[1] C[2] C[3] 20 Automatic Code Vectorization for (i=0; i < N; i++) C[i] = A[i] + B[i];Vectorized Code Scalar Sequential Code load load Iter. 1 add store load load Iter. 2 add 02/29/2020 store load load Time load Iter. 1 load add add store store Iter. 2
Vector Instruction Vectorization is a massive compile-time reordering of operation sequencing requires extensive loop dependence analysis 21 Vector Stripmining Problem: Vector registers have finite length Solution: Break loops into pieces that fit into vector registers, Stripmining 02/29/2020 22 Vector Instruction Parallelism Can overlap execution of multiple vector instructions example machine has 32 elements per vector register and 8 lanes Load Unit load Multiply Unit Add Unit mul
add time load mul add Instruction issue 02/29/2020 Complete 24 operations/cycle while issuing 1 short instruction/cycle 23 Vector Chaining Vector version of register bypassing introduced with Cray-1 LV V 1 v1 V
2 V 3 V 4 V 5 MULV v3,v1,v2 ADDV v5, v3, v4 Chain Load Unit Chain Mult. Add Memory 02/29/2020 24 Vector Chaining Advantage
Without chaining, must wait for last element of result to be written before starting dependent instruction Load Mul Time Add With chaining, can start dependent instruction as soon as first result appears Load Mul Add 02/29/2020 25 Vector Startup Two components of vector startup penalty functional unit latency (time through pipeline) dead time or recovery time (time before another vector instruction can start down pipeline) Functional Unit Latency R X X
X W R X X X W R X X X W R X X
X W R X X X W R X X X W R X
X X W R X X X W R X X X W R X
X X First Vector Instruction Dead Time 02/29/2020 Dead Time Second Vector Instruction W 26 Dead Time and Short Vectors No dead time 4 cycles dead time T0, Eight lanes No dead time 100% efficiency with 8 element vectors 64 cycles active
02/29/2020 Cray C90, Two lanes 4 cycle dead time Maximum efficiency 94% with 128 element vectors 27 Vector Scatter/Gather Want to vectorize loops with indirect accesses: for (i=0; i
Scatter example: for (i=0; i
Solution: Add vector mask (or flag) registers vector version of predicate registers, 1 bit per element and maskable vector instructions vector operation becomes NOP at elements where mask bit is clear Code example: CVM LV vA, rA SGTVS.D vA, F0 LV vA, rB SV vA, rA 02/29/2020 # Turn on all elements # Load entire A vector # Set bits in mask register where A>0 # Load B vector into A under mask # Store A back to memory under mask 30 Masked Vector Instructions Simple Implementation execute all N operations, turn off result writeback according to mask M[7]=1 M[6]=0 M[5]=1
M[4]=1 M[3]=0 A[7] A[6] A[5] A[4] A[3] B[7] B[6] B[5] B[4] B[3] M[2]=0 C[2] M[1]=1 C[1] Density-Time Implementation scan mask vector and only execute elements with non-zero masks M[7]=1 M[6]=0 M[5]=1
M[4]=1 M[3]=0 M[2]=0 M[1]=1 M[0]=0 A[7] B[7] C[5] C[4] C[1] Write data port M[0]=0 Write Enable 02/29/2020 C[0] Write data port 31 Compress/Expand Operations Compress packs non-masked elements from one vector register contiguously at start of destination vector register population count of mask vector gives packed vector length Expand performs inverse operation
M[7]=1 M[6]=0 M[5]=1 M[4]=1 M[3]=0 M[2]=0 M[1]=1 M[0]=0 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] A[7] A[5] A[4] A[1] A[7] A[5] A[4] A[1] Compress
A[7] B[6] A[5] A[4] B[3] B[2] A[1] B[0] M[7]=1 M[6]=0 M[5]=1 M[4]=1 M[3]=0 M[2]=0 M[1]=1 M[0]=0 Expand Used for density-time conditionals and also for general selection operations 02/29/2020 32 LV MULVS.D LV ADDVV.D
SV Convoys: 1 LV 2 LV 3 SV V1,Rx V2,V1,F0 V3,Ry V4,V2,V3 Ry,V4 ;load vector X ;vector-scalar multiply ;load vector Y ;add two vectors ;store the sum Vector Architectures Example: Convoys and Chimes MULVS.D ADDVV.D 3 chimes, 2 FP ops per result, cycles per FLOP = 1.5
For 64 element vectors, requires 64 x 3 = 192 clock cycles Copyright 2012, Elsevier Inc. All rights reserved. 33 Start up time Latency of vector functional unit Assume the same as Cray-1 Floating-point add => 6 clock cycles Floating-point multiply => 7 clock cycles Floating-point divide => 20 clock cycles Vector load => 12 clock cycles Vector Architectures Challenges
Optimizations: Multiple Lanes: > 1 element per clock cycle Vector Length Registers: Non-64 wide vectors Vector Mask Registers: IF statements in vector code Memory Banks: Memory system optimizations to support vector processors Stride: Multiple dimensional matrices Scatter-Gather: Sparse matrices Programming Vector Architectures: Program structures affecting performance Copyright 2012, Elsevier Inc. All rights reserved. 34 Element n of vector register A is hardwired to element n of vector register B
Allows for multiple hardware lanes Copyright 2012, Elsevier Inc. All rights reserved. Vector Architectures Multiple Lanes 35 Vector length not known at compile time? Use Vector Length Register (VLR) Use strip mining for vectors over the maximum length: Vector Architectures Vector Length Registers low = 0; VL = (n % MVL); /*find odd-size piece using modulo op % */ for (j = 0; j <= (n/MVL); j=j+1) { /*outer loop*/ for (i = low; i < (low+VL); i=i+1) /*runs for length VL*/ Y[i] = a * X[i] + Y[i] ; /*main operation*/ low = low + VL; /*start of next vector*/ VL = MVL; /*reset the length to maximum vector length*/ } Copyright 2012, Elsevier Inc. All rights reserved. 36 Consider: for (i = 0; i < 64; i=i+1) if (X[i] != 0) X[i] = X[i] Y[i]; Use vector mask register to disable elements (if conversion): Vector Architectures Vector Mask Registers LV V1,Rx ;load vector X into V1 LV V2,Ry ;load vector Y L.D F0,#0 ;load FP zero into F0 SNEVS.D V1,F0 ;sets VM(i) to 1 if V1(i)!=F0 SUBVV.D V1,V1,V2 ;subtract under vector mask SV Rx,V1 ;store the result in X GFLOPS rate decreases! Copyright 2012, Elsevier Inc. All rights reserved. 37 Memory system must be designed to support high bandwidth for vector loads and stores Spread accesses across multiple banks
Vector Architectures Memory Banks Control bank addresses independently Load or store non sequential words Support multiple vector processors sharing the same memory Example: 32 processors, each generating 4 loads and 2 stores/cycle Processor cycle time is 2.167 ns, SRAM cycle time is 15 ns How many memory banks needed? 32x6=192 accesses, 15/2.1677 processor cycles 1344! Copyright 2012, Elsevier Inc. All rights reserved. 38
Memory operations Load/store operations move groups of data between registers and memory Three types of addressing Unit stride Contiguous block of information in memory Fastest: always possible to optimize this Non-unit (constant) stride Harder to optimize memory system for all possible strides Prime number of data banks makes it easier to support different strides at full bandwidth Indexed (gather-scatter) Vector equivalent of register indirect Good for sparse arrays of data Increases number of programs that vectorize 02/29/2020 39 Interleaved Memory Layout Vector Processor Unpipelined DRAM Unpipelined DRAM
Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Addr Addr Addr Addr Addr Mod 8 Mod 8 Mod 8 Mod 8 Mod 8 =0 =2 =3 =4 =1 Addr Addr Addr Mod 8 Mod 8 Mod 8
=7 =6 =5 Great for unit stride: Contiguous elements in different DRAMs Startup time for vector operation is latency of single read What about non-unit stride? Above good for strides that are relatively prime to 8 Bad for: 2, 4 Better: prime number of banks! 02/29/2020 40 Consider: for (i = 0; i < 100; i=i+1) for (j = 0; j < 100; j=j+1) { A[i][j] = 0.0; for (k = 0; k < 100; k=k+1) A[i][j] = A[i][j] + B[i][k] * D[k][j]; } Must vectorize multiplication of rows of B with columns of D Use non-unit stride Bank conflict (stall) occurs when the same bank is hit faster than bank busy time: Vector Architectures Stride #banks / LCM(stride, #banks) < bank busy time (in # of cycles) Copyright 2012, Elsevier Inc. All rights reserved. 41 Example: 8 memory banks with a bank busy time of 6 cycles and a total memory latency of 12 cycles. How long will it take to complete a 64element vector load with a stride of 1? With a stride of 32? Answer: Vector Architectures Stride Stride of 1: number of banks is greater than the bank busy time, so it takes 12+64 = 76 clock cycles 1.2 cycle per element Stride of 32: the worst case scenario happens when the stride value is a multiple of the number of banks, which this is! Every access to memory will collide with the previous one! Thus, the total time will be: 12 + 1 + 6 * 63 = 391 clock cycles, or 6.1 clock cycles per element! Copyright 2012, Elsevier Inc. All rights reserved. 42 Consider sparse vectors A & C and vector indices K & M, and A and C have the same number (n) of non-zeros: for (i = 0; i < n; i=i+1) A[K[i]] = A[K[i]] + C[M[i]]; Ra, Rc, Rk and Rm the starting addresses of vectors Use index vector: LV Vk, Rk ;load K LVI Va, (Ra+Vk) ;load A[K[]] LV Vm, Rm ;load M LVI Vc, (Rc+Vm) ;load C[M[]] ADDVV.D Va, Va, Vc ;add them SVI (Ra+Vk), Va ;store A[K[]] Copyright 2012, Elsevier Inc. All rights reserved. Vector Architectures Scatter-Gather 43 Compilers can provide feedback to programmers Programmers can provide hints to compiler
Copyright 2012, Elsevier Inc. All rights reserved. Vector Architectures Programming Vec. Architectures 44 Optimizations: Multiple Lanes: > 1 element per clock cycle Vector Length Registers: Non-64 wide vectors Vector Mask Registers: IF statements in vector code Memory Banks: Memory system optimizations to support vector processors Stride: Multiple dimensional matrices Scatter-Gather: Sparse matrices Programming Vector Architectures: Program structures affecting performance Copyright 2012, Elsevier Inc. All rights reserved. Vector Architectures Summary of Vector Architecture 45
Properties of Vector Processors Each result independent of previous result => long pipeline, compiler ensures no dependencies => high clock rate Vector instructions access memory with known pattern => highly interleaved memory => amortize memory latency of over 64 elements => no (data) caches required! (Do use instruction cache) Reduces branches and branch problems in pipelines Single vector instruction implies lots of work ( loop) => fewer instruction fetches 02/29/2020 46 Advantages Vectors are inexpensive (O(N+NN2) circuitry) Vectors lower power One fetch and decode per instruction
Smaller code Vector unit switches off when not in use Vector instructions expose parallelism without speculation Copyright 2012, Elsevier Inc. All rights reserved. 47 Vector Architectures In-class exercise Consider the following code, which multiplies two vectors that contain single-precision complex values: For (i=0; i<300; i++) { c_re[i] = a_re[i] * b_re[i] a_im[i] * b_im[i]; c_im[i] = a_re[i] * b_im[i] a_im[i] * b_re[i]; Asumme that the processor runs at 700 MHz and has a maximum vector length of 64. A. B. C. What is the arithmetic intensity of this kernel (i.e., the ratio of floating-point operations per byte of memory accessed)?
Convert this loop into VMIPS assembly code using strip mining. Assuming chaining and a single memory pipeline, how many chimes are required? Copyright 2012, Elsevier Inc. All rights reserved. 48 A. B. This code reads four floats and writes two floats for every six FLOPs, so the arithmetic intensity = 6/6 = 1. Assume MVL = 64 300 mod 64 = 44 Copyright 2012, Elsevier Inc. All rights reserved. Vector Architectures In-class exercise 49 C. Identify convoys: 1. mulvv.slv # a_re * b_re
# (assume already loaded), # load a_im 2. lv mulvv.s # load b_im, a_im * b_im 3. subvv.ssv # subtract and store c_re 4. mulvv.slv # a_re * b_re, # load next a_re vector 5. mulvv.slv # a_im * b_re, # load next b_re vector 6. addvv.ssv # add and store c_im Vector Architectures In-class exercise 6 chimes Copyright 2012, Elsevier Inc. All rights reserved. 50 Media applications operate on data types narrower than
the native word size Example: disconnect carry chains to partition adder Limitations, compared to vector instructions: Number of data operands encoded into op code No sophisticated addressing modes (strided, scattergather) No mask registers Copyright 2012, Elsevier Inc. All rights reserved. SIMD Instruction Set Extensions for Multimedia SIMD Extensions 51 Implementations: Intel MMX (1996) Streaming SIMD Extensions (SSE) (1999)
Eight 16-bit integer ops Four 32-bit integer/fp ops or two 64-bit integer/fp ops Advanced Vector Extensions (2010) Eight 8-bit integer ops or four 16-bit integer ops Four 64-bit integer/fp ops Operands must be consecutive and aligned memory locations Generally designed to accelerate carefully written libraries rather than for compilers Advantages over vector architecture:
SIMD Instruction Set Extensions for Multimedia SIMD Implementations Cost little to add to the standard ALU and easy to implement Require little extra state easy for context-switch Require little extra memory bandwidth No virtual memory problem of cross-page access and page-fault Copyright 2012, Elsevier Inc. All rights reserved. 52 Example DXPY: L.D F0,a ;load scalar a MOV F1, F0 ;copy a into F1 for SIMD MUL MOV F2, F0 ;copy a into F2 for SIMD MUL MOV
F3, F0 ;copy a into F3 for SIMD MUL DADDIU R4,Rx,#512 ;last address to load Loop: L.4D F4,0[Rx] ;load X[i], X[i+1], X[i+2], X[i+3] MUL.4D F4,F4,F0 ;aX[i],aX[i+1],aX[i+2],aX[i+3] L.4D F8,0[Ry] ;load Y[i], Y[i+1], Y[i+2], Y[i+3] ADD.4D F8,F8,F4 ;aX[i]+Y[i], ..., aX[i+3]+Y[i+3] S.4D F8,0[Ry] ;store into Y[i], Y[i+1], Y[i+2], Y[i+3] DADDIU Rx,Rx,#32 ;increment index to X DADDIU Ry,Ry,#32 ;increment index to Y DSUBU R20,R4,Rx ;compute bound BNEZ R20,Loop ;check if done Copyright 2012, Elsevier Inc. All rights reserved. SIMD Instruction Set Extensions for Multimedia Example SIMD Code 53
Basic idea: Plot peak floating-point throughput as a function of arithmetic intensity Ties together floating-point performance and memory performance for a target machine Arithmetic intensity Floating-point operations per byte read Copyright 2012, Elsevier Inc. All rights reserved. SIMD Instruction Set Extensions for Multimedia Roofline Performance Model 54 Attainable GFLOPs/sec Min = (Peak Memory BW Arithmetic Intensity, Peak Floating Point Perf.) Copyright 2012, Elsevier Inc. All rights reserved. SIMD Instruction Set Extensions for Multimedia
Examples 55 Given the hardware invested to do graphics well, how can it be supplemented to improve performance of a wider range of applications? Basic idea: Heterogeneous execution model CPU is the host, GPU is the device Develop a C-like programming language for GPU
Graphical Processing Units Graphical Processing Units Compute Unified Device Architecture (CUDA) OpenCL for vendor-independent language Unify all forms of GPU parallelism as CUDA thread Programming model is Single Instruction Multiple Thread (SIMT) Copyright 2012, Elsevier Inc. All rights reserved. 56 A thread is associated with each data element Threads are organized into blocks Thread Blocks: groups of up to 512 elements
Multithreaded SIMD Processor: hardware that executes a whole thread block (32 elements executed per thread at a time) Blocks are organized into a grid CUDA threads, with thousands of which being utilized to various styles of parallelism: multithreading, SIMD, MIMD, ILP Graphical Processing Units Threads and Blocks Blocks are executed independently and in any order Different blocks cannot communicate directly but can coordinate using atomic memory operations in Global Memory GPU hardware handles thread management, not applications or OS A multiprocessor composed of multithreaded SIMD processors A Thread Block Scheduler Copyright 2012, Elsevier Inc. All rights reserved.
57 Copyright 2012, Elsevier Inc. All rights reserved. Graphical Processing Units Grid, Threads, and Blocks 58 Similarities to vector machines: Works well with data-level parallel problems Scatter-gather transfers Mask registers Large register files Graphical Processing Units NVIDIA GPU Architecture
Differences: No scalar processor Uses multithreading to hide memory latency Has many functional units, as opposed to a few deeply pipelined units like a vector processor Copyright 2012, Elsevier Inc. All rights reserved. 59 Multiply two vectors of length 8192 Code that works over all elements is the grid Thread blocks break this down into manageable sizes
512 elements/block, 16 SIMD threads/block 32 ele/thread Graphical Processing Units Example SIMD instruction executes 32 elements at a time Thus grid size = 16 blocks Block is analogous to a strip-mined vector loop with vector length of 32 Block is assigned to a multithreaded SIMD processor by the thread block scheduler Current-generation GPUs (Fermi) have 7-15 multithreaded SIMD processors Copyright 2012, Elsevier Inc. All rights reserved. 60 Figure 4.15 Floor plan of the Fermi GTX 480 GPU. This diagram shows 16 multithreaded SIMD Processors. The Thread Block Scheduler is highlighted on the left. The GTX 480 has 6 GDDR5 ports, each 64 bits wide, supporting up to 6 GB of capacity. The Host Interface is PCI Express 2.0 x 16. Giga Thread is the name of the scheduler that distributes thread blocks to Multiprocessors, each of which has its own SIMD Thread Scheduler. Copyright 2011, Elsevier Inc. All rights Reserved. 61
Threads of SIMD instructions Each has its own PC Thread scheduler uses scoreboard to dispatch No data dependencies between threads! Keeps track of up to 48 threads of SIMD instructions Graphical Processing Units Terminology Hides memory latency Thread block scheduler schedules blocks to SIMD processors Within each SIMD processor:
32 SIMD lanes Wide and shallow compared to vector processors Copyright 2012, Elsevier Inc. All rights reserved. 62 Figure 4.16 Scheduling of threads of SIMD instructions. The scheduler selects a ready thread of SIMD instructions and issues an instruction synchronously to all the SIMD Lanes executing the SIMD thread. Because threads of SIMD instructions are independent, the scheduler may select a different SIMD thread each time. Copyright 2011, Elsevier Inc. All rights Reserved. 63 NVIDIA GPU has 32,768 registers Divided into lanes Each SIMD thread is limited to 64 registers SIMD thread has up to:
Graphical Processing Units Example 64 vector registers of 32 32-bit elements 32 vector registers of 32 64-bit elements Fermi has 16 physical SIMD lanes, each containing 2048 registers Copyright 2012, Elsevier Inc. All rights reserved. 64 Figure 4.14 Simplified block diagram of a Multithreaded SIMD Processor. It has 16 SIMD lanes. The SIMD Thread Scheduler has, say, 48 independentthreads of SIMD instructions that it schedules with a table of 48 PCs. Copyright 2011, Elsevier Inc. All rights Reserved. 65 ISA is an abstraction of the hardware instruction set
Parallel Thread Execution (PTX) Uses virtual registers Translation to machine code is performed in software Example: one CUDA thread, 8192 of these created! Graphical Processing Units NVIDIA Instruction Set Arch. shl.s32R8, blockIdx, 9 ; Thread Block ID * Block size (512 or 29) add.s32 R8, R8, threadIdx ; R8 = i = my CUDA thread ID ld.global.f64 RD0, [X+R8] ; RD0 = X[i] ld.global.f64 RD2, [Y+R8] ; RD2 = Y[i] mul.f64 R0D, RD0, RD4 ; Product in RD0 = RD0 * RD4 (scalar a) add.f64 R0D, RD0, RD2 ; Sum in RD0 = RD0 + RD2 (Y[i]) st.global.f64 [Y+R8], RD0 ; Y[i] = sum (X[i]*a + Y[i]) Copyright 2012, Elsevier Inc. All rights reserved. 66
Like vector architectures, GPU branch hardware uses internal masks Also uses Branch synchronization stack Instruction markers to manage when a branch diverges into multiple execution paths Push on divergent branch and when paths converge Entries consist of masks for each SIMD lane I.e. which threads commit their results (all threads execute)
Graphical Processing Units Conditional Branching Act as barriers Pops stack Per-thread-lane 1-bit predicate register, specified by programmer Copyright 2012, Elsevier Inc. All rights reserved. 67 if (X[i] != 0) X[i] = X[i] Y[i]; else X[i] = Z[i]; ld.global.f64 setp.neq.s32 @!P1, bra RD0, [X+R8] ; RD0 = X[i] P1, RD0, #0 ; P1 is predicate register 1 ELSE1, *Push ; Push old mask, set new mask bits ; if P1 false, go to ELSE1 ld.global.f64 RD2, [Y+R8] ; RD2 = Y[i]
sub.f64 RD0, RD0, RD2 ; Difference in RD0 st.global.f64 [X+R8], RD0 ; X[i] = RD0 @P1, bra ENDIF1, *Comp ; complement mask bits ; if P1 true, go to ENDIF1 ELSE1: ld.global.f64 RD0, [Z+R8]; RD0 = Z[i] st.global.f64 [X+R8], RD0 ; X[i] = RD0 ENDIF1:
Each multithreaded SIMD processor also has local memory that is on-chip Graphical Processing Units NVIDIA GPU Memory Structures Shared by SIMD lanes / threads within a block only The off-chip memory shared by SIMD processors is GPU Memory Host can read and write GPU memory Copyright 2012, Elsevier Inc. All rights reserved. 69 Figure 4.18 GPU Memory structures. GPU Memory is shared by all Grids (vectorized loops), Local Memory is shared by all threads of SIMD instructions within a thread block (body of a vectorized loop), and Private Memory is private to a single CUDA Thread.
Copyright 2011, Elsevier Inc. All rights Reserved. 70 Each SIMD processor has Two SIMD thread schedulers, two instruction dispatch units 16 SIMD lanes (SIMD width=32, chime=2 cycles), 16 load-store units, 4 special function units Thus, two threads of SIMD instructions are scheduled every two clock cycles Graphical Processing Units Fermi Architecture Innovations
Fast double precision: gen- 78 515 GFLOPs for DAXPY Caches for GPU memory: I/D L1/SIMD proc and shared L2 64-bit addressing and unified address space: C/C++ ptrs Error correcting codes: dependability for long-running apps Faster context switching: hardware support, 10X faster Faster atomic instructions: 5-20X faster than genCopyright 2012, Elsevier Inc. All rights reserved. 71 Figure 4.19 Block Diagram of Fermis Dual SIMD Thread Scheduler. Compare this design to the single SIMD Thread Design in Figure 4.16. Copyright 2011, Elsevier Inc. All rights Reserved. 72 Copyright 2012, Elsevier Inc. All rights reserved. Graphical Processing Units Fermi Multithreaded SIMD Proc. 73 Focuses on determining whether data accesses in later iterations are dependent on data values produced in earlier iterations
Loop-carried dependence Example 1: for (i=999; i>=0; i=i-1) x[i] = x[i] + s; Detecting and Enhancing Loop-Level Parallelism Loop-Level Parallelism No loop-carried dependence Copyright 2012, Elsevier Inc. All rights reserved. 74 Example 2: for (i=0; i<100; i=i+1) { A[i+1] = A[i] + C[i]; /* S1 */ B[i+1] = B[i] + A[i+1]; /* S2 */ } S1 and S2 use values computed by S1 in previous iteration S2 uses value computed by S1 in same iteration Copyright 2012, Elsevier Inc. All rights reserved. Detecting and Enhancing Loop-Level Parallelism Loop-Level Parallelism 75 Example 3: for (i=0; i<100; i=i+1) { A[i] = A[i] + B[i]; /* S1 */ B[i+1] = C[i] + D[i]; /* S2 */ } S1 uses value computed by S2 in previous iteration but dependence is not circular so loop is parallel Transform to: A[0] = A[0] + B[0]; for (i=0; i<99; i=i+1) { B[i+1] = C[i] + D[i]; A[i+1] = A[i+1] + B[i+1]; } B[100] = C[99] + D[99]; Copyright 2012, Elsevier Inc. All rights reserved. Detecting and Enhancing Loop-Level Parallelism Loop-Level Parallelism 76 Example 4: for (i=0;i<100;i=i+1) { A[i] = B[i] + C[i]; D[i] = A[i] * E[i]; } No loop-carried dependence Example 5: for (i=1;i<100;i=i+1) { Y[i] = Y[i-1] + Y[i]; } Detecting and Enhancing Loop-Level Parallelism Loop-Level Parallelism Loop-carried dependence in the form of recurrence Copyright 2012, Elsevier Inc. All rights reserved. 77 Detecting and Enhancing Loop-Level Parallelism Finding dependencies Assume that a 1-D array index i is affine: a x i + b (with constants a and b)
An index in an n-D array index is affine if it is affine in each dimension Assume: Store to a x i + b, then Load from c x i + d i runs from m to n Dependence exists if: Given j, k such that m j n, m k n Store to a x j + b, load from a x k + d, and a x j + b = c x k + d Copyright 2012, Elsevier Inc. All rights reserved. 78 Detecting and Enhancing Loop-Level Parallelism Finding dependencies
Generally cannot determine at compile time Test for absence of a dependence: GCD test: If a dependency exists, GCD(c,a) must evenly divide (d-b) Example: for (i=0; i<100; i=i+1) { X[2*i+3] = X[2*i] * 5.0; } Answer: a=2, b=3, c=2, d=0 GCD(c,a)=2, d-b=3 no dependence possible. Copyright 2012, Elsevier Inc. All rights reserved. 79 Example 2: for (i=0; i<100; i=i+1) { Y[i] = X[i] / c; /* S1 */ X[i] = X[i] + c; /* S2 */ Z[i] = Y[i] + c; /* S3 */ Y[i] = c - Y[i]; /* S4 */ } Watch for antidependencies and output dependencies: RAW: S1S3, S1S4 on Y[i], not loop-carried WAR: S1S2 on X[i]; S3S4 on Y[i] WAW: S1S4 on Y[i] Copyright 2012, Elsevier Inc. All rights reserved. Detecting and Enhancing Loop-Level Parallelism Finding dependencies 80 Reduction Operation: for (i=9999; i>=0; i=i-1) sum = sum + x[i] * y[i];
Transform to for (i=9999; i>=0; i=i-1) sum [i] = x[i] * y[i]; for (i=9999; i>=0; i=i-1) finalsum = finalsum + sum[i]; Do on p processors: for (i=999; i>=0; i=i-1) finalsum[p] = finalsum[p] + sum[i+1000*p]; Note: assumes associativity! Copyright 2012, Elsevier Inc. All rights reserved. Detecting and Enhancing Loop-Level Parallelism Reductions 81
Demanding Ethical and Socially Responsible Behavior McGraw-Hill/Irwin Copyright
An increasing number of companies have adopted written codes of ethics. ETHICS CODES. 4-See Learning Goal 4: Distinguish between compliance-based and integrity-based ethics codes, and list the six steps in setting up a corporate ethics code.