# COSE221, COMP211 Logic Design Lecture 5. Verilog HDL COSE221, COMP211 Logic Design Lecture 5. Verilog HDL #1 Prof. Taeweon Suh Computer Science & Engineering Korea University Topics We are going to discuss the following topic s for roughly 3 weeks from today Introduction to Hardware Description Language (HDL) Combinational Logic Design with HDL Synchronous Sequential Logic Design with HDL Finite State Machine (FSM) Design Testbenches 2 Korea Univ Introduction In old days (~ early 1990s), hardware engineers used to draw schematic of digital logic (combinational and sequ ential logics), based on Boolean equations

But, it is not virtually possible to draw schematic as t he hardware complexity increases As the hardware complexity increases, there has been a necessity of designing hardware in a more efficient way 3 Korea Univ Examples Core i7 Number of transistors in Core i7 is roughl y 1 billion Assuming that the gate count is based on 2-input NAND gate, (which is composed o f 4 transistors), do you want to draw 250 million gates by hand? Absolutely NO T! Midterm Exam Even a simple FSM design problem in the midterm exam took you more than 30 mi nutes Even worse, many of you got your answe r wrong in the exam! 4

Korea Univ Introduction Hardware description language (HDL) Allows hardware designers to specify logic function using language So, hardware designer only needs to specify the target functionality (such as Boolean equations and FSM) with language Then, a computer-aided design (CAD) tool produces the optimized digital circuit with logic gates Nowadays, most commercial designs are built using HDLs HDL-based Design CAD Tool Optimized Gates module example( input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule 5

Korea Univ HDLs Two leading HDLs VHDL Developed in 1981 by the Department of Defense Became an IEEE standard (1076) in 1987 Verilog-HDL Developed in 1984 by Gateway Design Automation Became an IEEE standard (1364) in 1995 We are going to use Verilog-HDL in this class The book on the right is a good reference (but not re quired to purchase) IEEE: Institute of Electrical and Electronics Engineers is a professional society responsible for many computing standards including WiFi (802.11), Ethernet (802.3) etc 6 Korea Univ Hardware Design with HDL 3 steps to design hardware with HDL

1. Hardware design with HDL Describe target hardware with HDL When describing circuits using an HDL, its critical to think of the digital logic the code would produce 2. Simulation Validate the design Inputs are applied to the design Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware 3. Synthesis Transforms HDL code into a netlist, describing the hard ware

Netlist is a text file describing a list of logic gates and the wi res connecting them 7 Korea Univ CAD tools for Simulation There are renowned CAD companies that provide HDL simulators Cadence www.cadence.com Synopsys www.synopsys.com Mentor Graphics www.mentorgraphics.com We are going to use ModelSim Altera Starter Edition for simulation http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-i ndex.html 8 Korea Univ

CAD tools for Synthesis The same companies (Cadence, Synopsys, and Mentor Graphics) pr ovide synthesis tools, too They are extremely expensive to purchase though We are going to use a synthesis tool from Altera Altera Quartus-II Web Edition (free) Synthesis, place & route, and download to FPGA http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html 9 Korea Univ Verilog Modules Verilog Module A block of hardware with inputs and outputs Examples: AND gate, multiplexer, priority encoder etc A Verilog module begins with the module name and a list of the input s and outputs assign statement is used to describe combinational logic ~ indicates NOT & indicates AND | indicates OR a

b c Verilog Module y module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule 10 Korea Univ Synthesis Transforms HDL code into a netlist, that is, collection of gates and their connections module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & endmodule

11 c; Korea Univ Digital Design w/ Verilog HDL Combinational Logic Continuous assignment statement It is used to describe simple combinational logic assign always statement It is used to describe complex combinational logic always @(*) Synchronous Sequential Logic FSM is composed of flip-flops and combinational logics Flip-flops are described with always statement always @(posedge clk) always @(negedge clk) 12 Korea Univ Verilog Syntax

Verilog is case sensitive. So, reset and Reset are NOT the same signal. Verilog does not allow you to start signal or module names with numbers For example, 2mux is NOT a valid name Verilog ignores whitespace such as spaces, tabs and line breaks Proper indentation and use of blank lines are helpful to make your design readable Comments come in single-line and multi-line varieties like C-lan guage // : single line comment /* */ : multiline comment 13 Korea Univ Continuous Assignment Statem ent Statements with assign keyword Examples: assign y assign y

= ~(a & b); // NAND gate = a ^ b; // XOR gate It is used to describe combinational logic Anytime the inputs on the right side of the = changes in a st atement, the output on the left side is recomputed assign statement should not be used inside the always state ment 14 Korea Univ Bitwise Operators Bitwise operators perform a bit-wise operation on two operands Take each bit in one operand and perform the operation with the corresponding bit in the other operand module gates(input [3:0] a, b, output [3:0] y1, y2, y3, y4, y5); /* Five different two-input logic gates acting on 4 bit busses */

assign assign assign assign assign y1 y2 y3 y4 y5 = = = = = a & a | a ^ ~(a ~(a b; b; b;

& b); | b); // // // // // AND OR XOR NAND NOR endmodule 15 Korea Univ Wait! What is Bus? Bus is a medium that transfers data between computer components In hardware design, a collection of bits is called bus Example: A[3:0]: 4-bit bus (composed of A, A, A, A) A[5:0]: 6-bit bus

CPU D[63:0] Data Bus A[31:0] Address Bus North Bridge Main Memory South Bridge 16 Korea Univ Bus Representation Why uses a[3:0] to represent a 4-bit bus? How about a[0:3]? How about a[1:4] or a[4:1]? In digital world, we always count from 0 So, it would be nice to start the bus count from 0 If you use a[0:3],

a indicates MSB a indicates LSB If you use a[3:0], a indicates MSB a indicates LSB We are going to follow this convention in this course 17 Korea Univ Reduction Operators Reduction operations are unary Unary operation involves only one operand, whereas binary op eration involves two operands They perform a bit-wise operation on a single operand to produce a single bit result module and8(input [7:0] a, output y); assign y = &a; // &a is much easier to write than // assign y = a & a & a & a & // a & a & a & a;

endmodule As you might expect, |(or), &(and), ^(xor), ~&(nand), ~ |(nor), and ~^(xnor) reduction operators are available 18 Korea Univ Examples & 4b1001 & 4bx111 ~& 4b1001 ~& 4bx001 | 4b1001 ~| 4bx001 ^ 4b1001 ~^ 4b1101 ^ 4b10x1 = = = = = = =

= = 19 0 x 1 1 1 0 0 0 x Korea Univ Conditional Assignment The conditional operator ? : chooses between a secon d and third expression, based on a first expression The first expression is the condition If the condition is 1, the operator chooses the second expression If the condition is 0, the operator chooses the third expression Therefore, it is a ternary operator because it takes 3 inputs It looks the same as the C-language and Java, right? module mux2(input [3:0] d0, d1,

input s, output [3:0] y); assign y = s ? d1 : d0; // if s is 1, y = d1 // if s is 0, y = d0 What kind of hardware do you think this would generate? endmodule 20 Korea Univ Internal Variables It is often convenient to break a complex design i nto intermediate designs The keyword wire is used to represent internal va riable whose value is defined by an assign state ment For example, in the schematic below, you can declare p and g as wires s s

g cin cout a b p un1_cout 21 cout Korea Univ Internal Variables Example module fulladder(input wire p, g; a, b, cin, output s, cout); // internal nodes assign p = a ^ b; assign g = a & b;

assign s = p ^ cin; assign cout = g | (p & cin); endmodule s s g cin cout a b p un1_cout 22 cout Korea Univ Logical & Arithmetic Shifts Logical shift

Arithmetic shift 23 Korea Univ Logical & Arithmetic Shifts Logical shift (<<, >>) Every bit in the operand is simply moved by a given number of bit positions, and the vacant bit-positions are filled in with zeros Arithmetic shift (<<<, >>>) Like logical shift, every bit in the operand is moved by a given number of bit posi tions Instead of being filled with all 0s, when shifting to the right, the leftmost bit (usu ally the sign bit in signed integer representations) is replicated to fill in all the va cant positions This is sign extension Arithmetic shifts can be useful as efficient ways of performing multiplication or di vision of signed integers by powers of two a <<< 2 is equivalent to a x 4 ? a >>> 2 is equivalent to a/4? Take floor value if the result is not an integer. The floor value of X (or X) is the greatest integer nu mber less than or equal to X Examples:5/2 = 2, -3/2 = -2

24 Korea Univ Operator Precedence The operator precedence for Verilog is much like you would expect in other programming languages In particular, AND has precedence over OR You may use parentheses if the operation order is not clear Highes t Lowest ~ NOT *, /, % mult, div, mod +, - add,sub

<<, >> logical shift <<<, >>> arithmetic shift <, <=, >, >= comparison ==, != equal, not equal &, ~& AND, NAND ^, ~^ XOR, XNOR |, ~|

OR, XOR ?: ternary operator 25 Korea Univ Number Representation In Verilog, you can specify base and size of numbers Format: NBvalue N: size (number of bits) B: base (b: binary, d: decimal, o: octal, h: hexadecimal) When writing a number, specify both base and size Number # Bits Base Decimal Equivalen t

Stored 3b101 3 binary 5 101 8b11 8 binary 3 00000011 8b1010_10 11 8

binary 171 10101011 3d6 3 decimal 6o42 6 octal 8hAB 8 hexadecim al 26

6 34 171 110 100010 10101011 Korea Univ Replication Operator Replication operator is used to replicate a group of bits For instance, if you have a 1-bit variable and you want to repli cate it 3 times to get a 3-bit variable, you can use the replicati on operator wire [2:0] y; assign y = {3{b}}; // the above statement produces: // y = b b b 27

Korea Univ Concatenation Operator Concatenation operator { , } combines (concatenate s) the bits of 2 or more operands wire [11:0] y; assign y = {a[2:1], {3{b}}, a, 6b100_010}; // the above statement produces: // y = a a b b b a 1 0 0 0 1 0 // underscores (_) are used for formatting only to make it easier to read. Verilog ignores them. 28 Korea Univ Tri-state Buffer An implementation of tri-state buff er

E Y A A E E 0 0 1 1 A 0 1 0 1 Y Y Z Z 0 1

What happens to Y if E is 0? Output (Y) is effectively floating (Z) 29 Korea Univ Usage of Tri-state Buffer It is used to implement bus Only one device should drive the bus What happens if 2 devices drive the bus simultaneously? For example: Video drives the bus to 1, and Timer drives to 0 The result is x (unknown), indicating contention CPU Shared bus Video Ethernet 30 Timer Korea Univ

Tristate buffer and Floating output (Z) Verilog: module tristate(input [3:0] a, input en, output [3:0] y); assign y = en ? a : 4'bz; endmodule Synthesi s: en a[3:0] [3:0] [3:0] [3:0] [3:0] y[3:0]

y_1[3:0] 31 Korea Univ Verilog Module Description Two general styles of describing module functionali ty Behavioral modeling Express the modules functionality descriptively Structural modeling Describe the modules functionality from combination of si mpler modules 32 Korea Univ Behavioral Modeling Example Behavioral modeling Express the modules functionality descriptively module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b &

c; endmodule 33 Korea Univ Structural Modeling Example Structural modeling Describe the modules functionality from combination of simpler modules module myinv(input a, output y); assign y = ~a ; endmodule module myand3(input a, b, c, output y); assign y = a & b & c; endmodule module myor3(input a, b, c, output y); assign y = a | b | c; endmodule module example_structure (input a, b, c, output y); wire inv_a, inv_b, inv_c; wire and3_0, and3_1, and3_2; myinv inva (.a (a), .y (inv_a)); myinv invb (.a (b), .y (inv_b));

myinv invc (.a (c), .y (inv_c)); myand3 myand3 myand3 and3_y0 (.a (inv_a), .b (inv_b), .c (inv_c), .y (and3_0)); and3_y1 (.a (a), .b (inv_b), .c (inv_c), .y (and3_1)); and3_y2 (.a (a), .b (inv_b), .c (c), .y (and3_2)); myor3 or3_y (.a (and3_0), .b (and3_1), .c (and3_2), .y (y)); endmodule // Behavioral model module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & endmodule c; 34

Korea Univ Simulation module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & endmodule 35 c; Korea Univ Delays timescale directive is used to indicate the value of time unit The statement is of the form `timescale unit/precision Example: `timescale 1ns/1ps means that time unit is 1ns and simulation has 1p s precision In Verilog, a # symbol is used to indicate the number of time u nits of delay `timescale 1ns/1ps module example(input a, b, c,

output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule 36 Korea Univ Delays module example(input a, b, c, output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule 37

Korea Univ Testbenches Testbench is an HDL code written to test another HDL module, the device under test (dut) It is Not synthesizeable Types of testbenches Simple testbench Self-checking testbench Self-checking testbench with testvectors Well cover this later 38 Korea Univ Simple Testbench Signals in initial statement should be declared as reg (well cove r this later) `timescale y = bc + ab `timescale 1ns/1ps

module sillyfunction(input a, b, c, output y); assign #3 y = ~b & ~c | a & ~b; endmodule 1ns/1ps module testbench1(); reg aa, bb, cc; wire yy; // instantiate device under test sillyfunction dut(.a (aa), .b (bb), .c (cc), .y (yy)); // apply inputs one at a time initial begin aa = 0; bb = 0; cc = 0; #10; cc = 1; #10; bb = 1; cc = 0; #10; cc = 1; #10; aa = 1; bb = 0; cc = 0; #10; cc = 1; #10; bb = 1; cc = 0; #10; cc = 1; #10; end endmodule 39

Korea Univ Self-checking Testbench `timescale 1ns/1ps module testbench2(); y = bc + ab `timescale 1ns/1ps module sillyfunction(input a, b, c, output y); assign #3 y = ~b & ~c | a & ~b; endmodule reg aa, bb, cc; wire yy; // instantiate device under test sillyfunction dut(.a (aa), .b (bb), .c (cc), .y (yy)); // apply inputs one at a time // checking results

initial begin aa = 0; bb = 0; cc = 0; #10; if (yy !== 1) \$display("000 failed."); cc = 1; #10; if (yy !== 0) \$display("001 failed."); bb = 1; cc = 0; #10; if (yy !== 0) \$display("010 failed."); cc = 1; #10; if (yy !== 0) \$display("011 failed."); end endmodule 40 Korea Univ