# State Machines - Oakland University Finite State Machines Discussion D7.2 Mealy and Moore Machines Canonical Sequential Network s(t+1) next state State Register x(t) present input Combinational Network init clk s(t) present state

present z(t) output Mealy Machine s(t+1) C1 x(t) present input next state State Register init clk s(t) present state z(t)

C2 Moore Machine s(t+1) C1 x(t) present input next state State Register init clk z(t) s(t) present state C2

VHDL Canonical Sequential Network s(t+1) next state State Register x(t) present input Combinational Network init process(clk, init) clk process(present_state, x) s(t) present state

present z(t) output VHDL Mealy Machine process(present_state, x) s(t+1) C1 x(t) present input next state State Register init s(t) present state process(present_state, x)

clk process(clk, init) z(t) C2 VHDL Moore Machine s(t+1) C1 next state x(t) present input process(present_state, x) State Register init z(t) s(t) present

state C2 process(present_state) clk process(clk, init) Example Detect input sequence 1101 din clk fsm dout clr din dout 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 Use State Diagram

Detect input sequence 1101 0 S1 0 1 S0 0 CLR 0 S11 0 0 0 1 1 1 0

S1101 1 1 S110 0 fsm.vhd din clk fsm dout clr entity fsm is port (clk: in STD_LOGIC; clr: in STD_LOGIC; din: in STD_LOGIC; dout: out STD_LOGIC); end;

fsm.vhd architecture fsm_arch of fsm is type state_type is (S0, S1, S11, S110, S1101); signal present_state, next_state: state_type; begin s(t+1) C1 x(t) din next state clr State Register init present input clk z(t) s(t) present

state C2 dout fsm.vhd synch: process(clk, clr) begin if clr = '1' then present_state <= S0; elsif clk'event and clk = '1' then present_state <= next_state; end if; end process; s(t+1) C1 x(t) din next state clr

State Register init present input clk z(t) s(t) present state C2 dout fsm.vhd comb1: process(present_state, din) begin case present_state is 0 when S0 => 1 S0 if din = '1' then

0 0 next_state <= S1; else 0 CLR 0 next_state <= S0; S1101 end if; 1 when S1 => 1 if din = '1' then next_state <= S11; else next_state <= S0; end if; S1 0 1 S11 0

1 S110 0 0 1 fsm.vhd when S11 => if din = '0' next_state else next_state end if; when S110 => if din = '1' next_state else next_state end if; when S1101 => if din = '0' next_state else next_state

end if; when others => null; end case; end process; then <= S110; 0 S0 0 <= S11; then <= S1101; <= S0; then <= S0; <= S11; CLR 0 S1101 1

S1 0 1 0 0 1 1 S11 0 1 S110 0 0 1 fsm.vhd end fsm_arch;

s(t+1) C1 x(t) din next state State Register comb2: process(present_state) begin if present_state = S1101 then dout <= '1'; else dout <= '0'; end if; end process; init clr present input clk z(t)

s(t) present state C2 dout fsmx.vhd LD(0) LD(1) din clr BTN(3) clk BTN(1) BTN(0) mclk bn clkdiv

clk_pulse cclk dout fsm fsmx LD(7) fsmx.vhd entity fsmx is port( mclk : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(7 downto 0); BTN : in STD_LOGIC_VECTOR(3 downto 0); LD : out STD_LOGIC_VECTOR(7 downto 0); AtoG : out STD_LOGIC_VECTOR(6 downto 0); dp : out STD_LOGIC; AN : out STD_LOGIC_VECTOR(3 downto 0) ); end fsmx; fsmx.vhd architecture fsmx of fsmx is component fsm

port( clk : in std_logic; clr : in std_logic; din : in std_logic; dout : out std_logic); end component; fsmx.vhd component clock_pulse port( inp : in std_logic; cclk : in std_logic; clr : in std_logic; outp : out std_logic); end component; signal clr, clk, cclk, bn: std_logic; signal clkdiv: std_logic_vector(23 downto 0); fsmx.vhd bn <= BTN(1) or BTN(0); clr <= BTN(3); U0: clk_pulse port map (inp => bn, cclk => cclk, clr =>clr, clk => clk);

U1: fsm port map (clr =>clr, clk => clk, din => BTN(1), dout => LD(7)); LD(0) <= BTN(0); LD(1) <= BTN(1); Detect input sequence 1101