The MCF51JM Microcontroller

The MCF51JM Microcontroller

2: The MCF51JM Microcontroller CET360 Microprocessor Engineering J. Sumey ver. 1/30/18 MCF51JM Overview 32-bit ColdFire (V1) MCU w/ USB descendent of the 68000 (68k) family, now a NXP product same register set based on high-performance RISC CPU 2.7~5.5V, up to 50 MHz

32-bit data bus, PC, registers, ALU! 24-bit address bus 2-stage pipelines for each instructions and operands 2 operational modes: user, supervisor extensive library of on-board peripheral modules multiple operational modes single-wire background debug capability (BDM) 2 MCF51JM Modules Memory: Flash (128KB), RAM (16KB) ACMP: analog comparator ADC: 12-bit analog-to-digital (12 channels) BDM: background debug support, single-wire CAN: controller area network CMT: carrier modulator timer COP: computer operating properly IIC: inter-integrated circuit serial bus KBI: keyboard interrupt (8 inputs)

LVD: low voltage detector MCG: multipurpose clock generator GPIO: I/O ports (51 GP + 6 Rapid GP pins) RTC: real-time counter SCI, SPI: serial interfaces (2 SCI, 2 SPI) TPM: timer/pulse-width modulator (6+2 channels) USBOTG: host/device support (dual-role) 3 4 MCF51JM Packages available in QFP, LQFP packages 44, 64, 80 pins Firebird32 uses 64-pin version on a 40-pin DIP module 5 Memory Map MCU is von Neumann

RAM, ROM, IO Registers exist in single map 24-bit address bus -> 16 MB address space 128K FLASH: 0x00_0000..0x01_FFFF includes vectors 16K RAM: 0x80_0000..0x80_3FFF IO Registers: 0xFF_8000..0xFF_FFFF see Reference Manual 6 ColdFire CPU performs all computation / instruction execution (CFPRM ColdFire Programmers Ref. Manual) Programming Model User Mode Condition Code Register

X: sign extend N: Negative flag Z: Zero flag V: signed overflow C: unsigned overflow 16 general-purpose 32-bit registers (8 Data + 8 Address) 32-bit program counter, PC (top 8 bits forced to zero) 8-bit condition code register, CCR A7 doubles as SP this is User mode, Supervisor mode has additional 8 Programming Model - Supervisor adds additional CPU registers for "privileged" operations MCF51JM includes: 16-bit status register, SR (CCR is lower byte) supervisor SP, OTHER_A7 VBR sets base address of vector table (defaults to 0)

9 Status Register (SR) Details system byte only available in supervisor mode T: 1=trace enable S: 0=user mode, 1=supervisor mode M: 1=master state, 0=interrupt state I: sets interrupt mask level 0..7 0 = all interrupts enabled 1 = all interrupts disabled (except IRQ pin) 10 Instruction Format word = 16 bits (32 bits = longword) first word is instruction op word specifies operation, instruction length, EA mode

additional words specify operands 11 ColdFire Addressing Modes Addr. Mode Generation Description Immediate Operand given Operand is byte, word, or longword after opword (use # in assembly) Absolute Short EA given 16-bit operand EA follows instruction opword Absolute Long EA given 32-bit operand EA follows instruction opword Data Register Direct EA=Dn Operand is in a Data register Address Register

Direct EA=An Operand is in an Address register Address Register Indirect EA=(An) Address Register Indirect with Postincrement EA=(An); An += Size Address register contains EA of operand & gets incremented after use Address Register Indirect with Predecrement An -= Size; EA=(An) Address register is first decremented then contains EA of operand Address Register Indirect with Displacement EA = (An) +d16

Operand address is sum of address register plus 16-bit signed displacement Program Counter Indirect with Displacement EA = (PC) +d16 Operand address is sum PC plus 16-bit signed displacement Address register contains EA of operand 12 ColdFire Instruction Set Summary organized by type of operation data movement program control integer arithmetic floating-point arithmetic (when FPU available)

logical operations shift operations bit manipulation system control cache maintenance 13 Parallel I/O Ports provides interface to general purpose I/O pins (MCF51JM ColdFire Ref. Manual, ch. 9) I/O Ports up to 70 i/o pins on up to 9 ports each 8-bit port has i/o register and DDR also have pull-up, slew rate, drive strength, and interrupt control registers naming convention: PTxD, PTxDD named A..I

ex: PTAD, PTEDD ref: table 4-2 in ref. manual also: individual bit access ex: PTBD_PTBD2 = 1; 15 Real-Time Counter (RTC) Module provides hardware time counting functions with optional interrupt (MCF51JM ColdFire Ref. Manual, ch. 17) RTC Components strictly internal, no external pins three input clock sources, software selectable 1 kHz internal low-power oscillator (LPO) 32 kHz internal clock (IRCLK) external clock (ERCLK) from MCG module software-programmable prescaler 8-bit up counter with 8-bit modulo

match comparator software controlled interrupt on modulo match 17 RTC Block Diagram shaded boxes represent RTC registers 18 RTC Register Summary only three 8-bit registers: RTCSC = RTC Status and Control register RTCCNT = 8-bit RTC Counter register RTCMOD = 8-bit Modulo register all registers default to 0 19 RTC Status / Control Register RTIF (b7): Real-Time Interrupt Flag RTCLKS (b6-5): Real-Time Clock Source Select

chooses RTC clock input source 00=LPO, 01=ERCLK, 1x=IRCLK RTIE (b4): Real-Time Interrupt Enable sets when counter reaches modulo register clear by writing a 1 enables RTC interrupts to CPU (when 1) RTCPS (b3-0): Real-Time Clock Prescaler Select chooses binary- or decimal-based divide-by values see table in ref. manual; note: 0000=Off 20 RTC Usage Example msdelay(): a precise ms delay function // msdelay(): delay given number of milliseconds using Real-Time Counter module void msdelay(int n) { while (n-- > 0) { byte ctr = RTCCNT; // take copy of current RTC Counter register while (RTCCNT == ctr) {} // wait till it changes

} } // include in initialization code: RTCSC = 0x08; // enable RTC, select 1ms period from 1kHz internal clock requires RTCMOD > 0 this version does not use RTIF leaving the RTC modulo feature fully available 21 INTerrupt Controller (INTC) Module prioritizes all system exceptions and performs all vector handling (MCF51JM Coldfire Ref. Manual, ch. 8 and ColdFire Programmers Ref. Manual, ch. 11) Exception Handling Exception: an unscheduled (but sometimes planned) event that causes the CPU to depart (i.e. abort) from the normal fetch-decodeexecute cycle may or may not be fault related Exception processing: 1. copy the Status Register (SR) then set SR[S] to switch to supervisor mode 2. determine the appropriate exception vector number

based on source/cause of exception 3. save current context (PC, SR) in an 8-byte exception frame on the system stack (A7) 4. fetch to PC address of exception handler from vector table; resume normal instruction processing 5. exception handler must end with RTE instruction, after which the interrupted instruction is restarted 23 Vector Table ColdFire vector table up to 256 vectors, 4-bytes each each vector contains address of respective exception handler first 64 for CPU, 192 for other uses Vector Base Register (VBR) points to begin of table this is a supervisor mode register by default, table begins at location 0

i.e. peripheral/software/etc. uses 1st 1 KiB of memory map MCF51JM exceptions: defines 64 for CPU + 39 for peripheral IRQs (103 total) 24 ColdFire Exception Vectors (1/2) Vector Number Vector Offset 0 000 Initial stack pointer 1 004 Initial program counter 2 008 Access error

3 00C Address error 4 010 Illegal instruction 5 014 Divide by zero 6-7 018-01C 8 020 Privilege violation 9 024 Trace 10 028

Unimplemented line-A opcode 11 02C Unimplemented line-F opcode 12 030 Non-PC breakpoint debug interrupt 13 034 PC breakpoint debug interrupt 14 038 Format error 15 03C Uninitialized interrupt Assignment Reserved 25

ColdFire Exception Vectors (2/2) Vector Number Vector Offset 16-23 040-05C 24 060 25-31 064-07C Level 1-7 autovectored interrupts 32-47 080-0BC Trap #0-15 instructions 48 0C0 Floating-point branch on unordered condition 49 0C4

Floating-point inexact result 50 0C8 Floating-point divide-by-zero 51 0CC Floating-point underflow 52 0D0 Floating-point operand error 53 0D4 Floating-point overflow 54 0D8 Floating-point input not-a-number (NAN) 55 0DC Floating-point input denormalized number

56-60 0E0-0F0 61 0F4 62-63 0F8-0FC Reserved 64-255 100-3FC User-defined interrupts (I/O peripherals) Assignment Reserved Spurious interrupt Reserved Unsupported instruction 26 MCF51JM Exceptions (1/2) Vector Number Vector Offset 64

100 IRQ (pin) 65 104 Low Voltage Detect 66 108 Loss of Lock 67 10C SPI1 68 110 SPI2 69 114 USB_Status 70 118

- 71 11C TPM1 Channel 0 72 120 TPM1 Channel 1 73 124 TPM1 Channel 2 74 128 TPM1 Channel 3 75 12C TPM1 Channel 4 76 130 TPM1 Channel 5

77 134 TPM1 Overflow 78 138 TPM2 Channel 0 79 13C TPM2 Channel 1 80 140 TPM2 Overflow Assignment 27 MCF51JM Exceptions (2/2) Vector Number Vector Offset 81

144 SCI1 Error 82 148 SCI1 Receive 83 14C SCI1 Transmit 84 150 SCI2 Error 85 154 SCI2 Receive 86 158 SCI2 Transmit 87 15C

KBI Interrupt 88 160 ADC Conversion 89 164 ACMP 90 168 IIC1 91 16C RTC 92 170 IIC2 93 174 CMT

94 178 CAN Wakeup 95 17C CAN Error 96 180 CAN Receive 97 184 CAN Transmit 98 188 RNGA Error 104-110 1A0-1BC Assignment Force_lvli (i=7..1)

28 Interrupt Dispositions some interrupts are non-maskable but most are maskable CPU CCR contains a 3-bit interrupt priority field for controlling maskable interrupts 0..7, any level below current setting is disabled resets to 7 CodeWarriors hidef.h file contains relevant macros programmer can enable / disable at will EnableInterrupts: sets level to 0 DisableInterrupts: sets level to 7 derivative.h defines all vector numbers ex: #define VectorNumber_Vrtc

91U 29 Spoiler alert! (how to program an ISR) ex: an ISR to handle RTC interrupts must also enable interrupts in the RTCSC register, i.e. RTIE must be set! // rtc_isr(): process interrupts from RTC module interrupt VectorNumber_Vrtc void rtc_isr(void) { RTCSC_RTIF = 1; // acknowledge & reset RTIF flag // process RTC event timekeeping, update LEDs, etc. } ISRs can neither accept or return arguments "interrupt" causes '}' to be an RTE instead of RTS 30 Timer/PWM (TPM) Module a highly flexible peripheral module used to perform timing-related tasks in hardware (MCF51JM ColdFire Ref. Manual, ch. 22) TPM Features

two TPMs optionally uses PortE,F bits for external I/O input capture measure characteristics of input pulses/signals output compare TPM1 has 6 channels, TPM2 has 2 generation of programmer-defined signals pulse/periodic, frequency, duty cycle powerful interrupt capabilities 32 TPM Components 16-bit binary up counter driven by BUSCLK thru with programmable

prescaler 8 choices: 1 .. 128 up to 8 channels, ea. 16-bits, programmable for input capture (IC) or output compare (OC) operation PWM generation capability set of control/status registers 33 TPM Block Diagram TPM Register Summary Register Name Notes TPMxSC Description Function TPM Status and Control Register

primary status / control functions: clock source select, prescale factor select, timer overflow interrupt enable TPMxCNT 1 TPM Counter Register 16-bit binary up counter TPMxMOD 1 TPM Counter Modulo Register sets modulo value for CNT counter register TPMxCnSC 2 TPM Channel n Status / Control Register per channel status/control functions: mode select, edge/level select, channel interrupt enable TPMxCnV 1,2

TPM Channel Value Register CNT value at Input Capture or Output Compare event Notes: 1) are 16-bit registers but also support H/L-byte access 2) repeat for as many channels as available 35 TPM Interrupts Interrup t Local Enable Source TOF TOIE (TPMxSC) Timer overflow Timer Overflow interrupt CHnF CHnIE (TPMxCnSC) Channel event Input capture or output compare event occurred on channel n

Description Notes: - each channel has its own interrupt vector 36 ADC Module a peripheral module providing 28 channels of 8-, 10- or 12-bit A/D conversion (MCF51JM ColdFire Ref. Manual, ch. 21) ADC Features 28 input channels (12 externally available) 8-, 10- or 12-bit resolution right justified, unsigned result selectable ADC clock conversion time under 2 us possible! per command or continuous conversion modes internal temperature sensor

one interrupt source conversion complete 38 ADC Module Components conversion clock selection & prescaler 32 inputs via analog multiplexer successive approx. register (SAR) compare function interrupt logic 39 ADC Block Diagram 40 ADC Register Map Address Offset Register Name Function 0x0000 ADCSC1

Status and Control Register 1 selects channel, conversion mode, interrupt enable; provides conversion complete status (COCO) 0x0001 ADCSC2 Status and Control Register 2 sets conversion trigger and compare features 0x0002 ADCRH Data Result High Register top 2 (10-bit) or 4 (12-bit) bits of ADC result 0x0003 ADCRL Data Result Low Register bottom 8 bits of ADC result 0x0004 ADCCVH Compare Value High Register high byte of compare value (when enabled)

0x0005 ADCCVL Compare Value Low Register low byte of compare value (when enabled) 0x0006 ADCCFG Configuration Register selects ADC clocking, sample time, # bits (8,10,12) 0x0007 APCTL1 Pin Control 1 Register disables pin I/O control, channels 0-7 0x0008 APCTL2 Pin Control 1 Register disables pin I/O control, channels 8-15 Description Above addresses are offsets from ADC base address (0xFFFF8010). 41

ADC Channel Assignments (MCF51) ADCH* Channel 00000 AD0 00001 Input ADCH* Channel PTB0/MISO2/ADP0 10000 AD16 VREFL AD1 PTB1/MOSI2/ADP1 10001 AD17 VREFL 00010

AD2 PTB2/SPSCK2/ADP2 10010 AD18 VREFL 00011 AD3 PTB3/SS2/ADP3 10011 AD19 VREFL 00100 AD4 PTB4/KBIP4/ADP4 10100 AD20 VREFL 00101 AD5

PTB5/KBIP5/ADP5 10101 AD21 VREFL 00110 AD6 PTB6/ADP6 10110 AD22 Reserved 00111 AD7 PTB7/ADP7 10111 AD23 Reserved 01000 AD8 PTD0/ADP8/ACMP+

11000 AD24 Reserved 01001 AD9 PTD1/ADP9/ACMP- 11001 AD25 Reserved 01010 AD10 PTD3/KBIP3/ADP10 11010 AD26 Temperature Sensor 01011 AD11 PTD4/ADP11 11011

AD27 Internap bandgap 01100 AD12 VREFL 11100 - 01101 AD13 VREFL 11101 VREFH VDD 01110 AD14 VREFL 11110 VREFL VSS

01111 AD15 VREFL 11111 ADC off *bottom 5 bits written to the ADCSC1 register Input Reserved None 42 ADC Application (no compare) initialization or per conversion: select ADC clock source & divide-by, # bits for conversion (ADCCFG) set pin control register bit(s) to switch between port i/o or ADC function ADPCx: 0=port i/o, 1=A/D function

per conversion: select channel to convert (ADCSC1) wait for conversion complete (COCO) read data from result registers (ADCRx) 43 ADC Example #include mcf51jm128.h // ADC initialization: ADCCFG = ??? + ???; ADPC1_ADPC4 = ?; // select Busclk/4 // 10-bit mode // select A/D for channel 4 pin // perform conversion ADCSC1 = ?; while (!ADCSC1_COCO){} int adcresult = ADCR; // start conversion on PTB4 // wait for conversion complete* // grab 2-byte result *can also use WAITFOR macro here! i.e.: WAITFOR(ADCSC1_COCO); 44 SCI Module implements full duplex,

asynchronous serial communication at programmed baud rates with framing (MCF51JM ColdFire Ref. Manual, ch. 12) SCI Features configurable baud rate 8- or 9-bit data format although shared through 3 common vectors uses pins on Ports C,E parity, noise, framing errors 10 interrupt events for multi-node communications receiver error detection

supports standard asynchronous rates most MCF members have multiple SCIs! implements a total of 7 r/w registers 46 SCI Components 13-bit baud rate divider transmitter w/ 11-bit PISO shift register determines data rate for both Tx & Rx serializes output data to TxD with framing parity generator 2 interrupt events shared on SCI Transmit vector receiver w/ 11-bit SIPO shift register deserializes input data from RxD 4 rx interrupt events on SCI Receive vector 4 error events on SCI Error vector

47 SCI Transmitter Block Diagram 48 49 SCI Receiver Block Diagram SCI Register Map Address Offset Register Name Description 0 SCIxBDH SCI Baud rate register High 1 SCIxBDL SCI Baud rate register Low 2 SCIxC1 SCI Control Register 1

3 SCIxC2 SCI Control Register 2 4 SCIxS1 SCI Status Register 1 5 SCIxS2 SCI Status Register 2 6 SCIxC3 SCI Control Register 3 7 SCIxD SCI Data Register (Tx/Rx) Above addresses are offsets from SCI base address. SCI1 base address = 0xFFFF8038

SCI2 base address = 0xFFFF8040 50 Baud Rate Setting baud rate is determined from BUSCLK and 13 SBR bits divider in Baud rate register: SCI Baud = BUSCLK / (16 SBR[12:0]) BUSCLK = BUSCLK = Baud % Error % Error 12MHz 16MHz example SBR values: 2400 313 -0.16 417 -0.08 4800 156 0.16 208 0.16

9600 78 0.16 104 0.16 19200 39 0.16 52 0.16 38400 20 -2.34 26 0.16 51 NRZ Serial Data Format Non Return to Zero

format determined by SCIxC1 bits: 7 6 5 4 3 2 1 0 LOOPS SCISW RSRC M Wake ILT PE

PT M: mode (0=1/8/1, 1=1/9/1) PE: parity enable (0=off, 1=on) PT: parity type (0=even, 1=odd) 52 SCI Interrupts 1/3 SCI can generate interrupts for any of 4 different events as enabled in SCIxC2 (top 4 IE bits): 7 6 5 4 3 2 1 0 TIE TCIE RIE IDIE

TE RE RWU SBK Transmit, Transmit Complete share SCI Transmit vector Receive, Idle share SCI Receive vector also: SCI transmitter & receiver must be turned on! by setting TE & RE (Enable) bits 53 SCI Interrupts 2/3 error interrupts for any of 4 different error events as enabled in SCIxC3 (bottom 4 IE bits):

7 6 5 4 3 2 1 0 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE overrun, noise error, framing error, parity error shared on SCI Error vector 54

SCI Interrupts 3/3 ISR must check SCIxS1 to determine cause of interrupt and react appropriately (only for multiple enabled events) top 4 6bits 7 5 TDRE TC RDRF 4 3 2 1 0 IDLE OR NF

FE PF bottom 4 bits reflect error status of previously received character 55 SCI Operation 1/2 initialization write baud registers set baud rate SCIxBDH first, then SCIxBDL can also just write 16 bit word to SCIxBD write SCIxC1 to set data format write SCIxC2 to turn on SCI & enable Tx/Rx interrupts as appropriate optional: write SCIxC3 to turn on error interrupts if needed also make sure SCI vectors are setup if using SCI interrupts! 56

SCI Code: Initialization activate SCI for 9600 baud (at 16 MHz bus) (and no interrupts) // SCI initialize routine void SCI1_init() { SCI1BD = ???; // set baud rate SCI1C1 = ???; // no special settings needed SCI1C2 = ???; // enable Tx & Rx } 57 SCI Operation 2/2 transmission wait for transmitter empty write new character to SCIxD reception

wait for character to be received TDRE=1 of SCIxS1 RDRF=1 in SCIxS1 read received char from SCIxD Note: this approach will block the CPU! what if blocking is not desired? 58 SCI Code: Single Byte I/O void SCI1_putc(char c) // SCI output routine { if (c == '\n') SCI_putc('\r'); // auto CR on LF while (!(SCI1S1_TDRE)) {} // wait for SCI Tx ready SCI1D = c; // send the char } char SCI1_getc() // SCI input { char stat, chr; while (!(SCI1S1_RDRF)) {} //

stat = SCI1S1 & 0xf; // chr = SCI1D; // if (stat != 0) chr = '?'; // return chr; // } routine wait for received char check for OR,NF,FE,PE read received SCI char error check return received char 59 SCI Code: String Output void SCI1_puts(char *s) { while (*s) SCI1_putc(*s++); } // SCI string output routine // while *s not terminating null, // output 1 char & advance pointer 60

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