EE666 Advanced Semiconductor Devices Tunneling Devices Dane Wheeler April 19, 2005 EE666 Advanced Semiconductor Devices Tunneling Devices Dane Wheeler April 19, 2005 Outline Motivation
Band-to-Band Tunneling Device Proposals Fabrication Techniques Notre Dame Devices Conclusions Motivation Scaling: some proposed tunneling field effect transistor (TFET) designs do not suffer from short channel effects Power Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETs Design Flexibility: Circuits can be made with fewer devices Obligatory Moores Law human brain in 2012? Reference http://www.intel.com/research/silicon/mooreslaw.htm
Whats so great about a tunneling device? Lower sub-threshold swing can allow for lower operating voltages to be used Negative differential resistance (NDR) properties can be exploited to create simpler designs for bi-stable circuits, differential comparators, oscillators, etc. Leads to chips that consume less power Tunneling Tunneling is a quantum mechanical phenomenon with no analog in classical physics Occurs when an electron passes through a potential barrier without having enough energy to do so (Esaki) Tunnel Diode (TD) Simplest tunneling device
Heavily-doped pn junction EF Leads to overlap of conduction and valence bands Carriers are able to tunnel inter-band Tunneling goes exponentially with tunneling distance Requires junction to be abrupt EC EV Band-to-Band Tunneling in a Tunnel Diode (c) (e) I
(b) (d) V EC (a) EV EF (a) (b) (c) (d) (e)
Figures of Merit Peak current 100 kA/cm2 Peak-to-Valley Ratio (PVR) I V Bi-stable Configuration V I D1 X D2 X1
X2 V TD Differential Comparator V CC D3 M3 X D4 CK M4 D1 D2
VOUT VOUT VIN RL M1 M 2 I1 VIN RL I2 ITAIL VEE Direct vs. Indirect Tunneling
Direct Indirect Indirect materials require phonons to tunnel, thus reducing the probability of a tunneling event Tunnel Current Expressions m*1/ 2 EG3 / 2 2 Et exp T exp E 2 2eF E 4 2eF *
3 m EG 4 2m *E g q m * Va Jt exp( 1 / 2 2 2 3q 4 2 E g 3 1/ 2 3/ 2 ) 1 dVeff B d 1
S ln10( 2 ) Veff dVgs dVgs Lateral TFET Proposed by our own Qin Zhang Can theoretically beat 60 mV/decade subthreshold swing G S x ox y p+ Si L tox W
BOX n+ Si tSi D Lateral TFET Off State On State Another Lateral TFET Proposed by A. Zaslavsky in SOI, although original idea from Shockley Gate placed on top of depletion region GATE N+ P+
OX Si More about AZ TFET Double Lateral TFET Acts as back-to-back TD pair at 0 gate bias Gate bias of either polarity will break tunneling condition GATE N+ P+ OX Si N+
Fabrication Techniques As mentioned earlier, heavily-doped, abrupt junctions are needed Can be obtained using several different methods Ion implantation Rapid thermal diffusion Molecular beam epitaxy Laser diffusion Doping by Rapid Thermal Processor Approach: Rapid thermal diffusion Spin-on diffusants 100 mm wafers IC-compatible processes Modular Process Technology RTP-600S
0.6 Voltage (V) 0.8 1 Wafer: W22 TDs with Oxide Window Process 0.3 2 J = 266 A/cm p PVR = 2.15 Current (mA)
First demonstration of tunnel diodes on high resistivity 1 5 k cm substrates 0.2 0.1 0 High resistivity substrate 1-5 k cm -0.1 Enables microwave characterization
-0.2 -0.2 Y140, (5,3)(2,1), 4 x 16 m 0 0.2 0.4 Voltage (V) 0.6 2 0.8 Conclusions Tunnel diodes are expected to add
another node in the road Three-terminal tunnel devices could add several nodes at the end of CMOS-scaling Challenges facing TFETs are more practical than theoretical Lithography, SOI process optimization
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