Tunneling Devices - University of Notre Dame

EE666 Advanced Semiconductor Devices Tunneling Devices Dane Wheeler April 19, 2005 EE666 Advanced Semiconductor Devices Tunneling Devices Dane Wheeler April 19, 2005 Outline Motivation

Band-to-Band Tunneling Device Proposals Fabrication Techniques Notre Dame Devices Conclusions Motivation Scaling: some proposed tunneling field effect transistor (TFET) designs do not suffer from short channel effects Power Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETs Design Flexibility: Circuits can be made with fewer devices Obligatory Moores Law human brain in 2012? Reference http://www.intel.com/research/silicon/mooreslaw.htm

Whats so great about a tunneling device? Lower sub-threshold swing can allow for lower operating voltages to be used Negative differential resistance (NDR) properties can be exploited to create simpler designs for bi-stable circuits, differential comparators, oscillators, etc. Leads to chips that consume less power Tunneling Tunneling is a quantum mechanical phenomenon with no analog in classical physics Occurs when an electron passes through a potential barrier without having enough energy to do so (Esaki) Tunnel Diode (TD) Simplest tunneling device

Heavily-doped pn junction EF Leads to overlap of conduction and valence bands Carriers are able to tunnel inter-band Tunneling goes exponentially with tunneling distance Requires junction to be abrupt EC EV Band-to-Band Tunneling in a Tunnel Diode (c) (e) I

(b) (d) V EC (a) EV EF (a) (b) (c) (d) (e)

Figures of Merit Peak current 100 kA/cm2 Peak-to-Valley Ratio (PVR) I V Bi-stable Configuration V I D1 X D2 X1

X2 V TD Differential Comparator V CC D3 M3 X D4 CK M4 D1 D2

VOUT VOUT VIN RL M1 M 2 I1 VIN RL I2 ITAIL VEE Direct vs. Indirect Tunneling

Direct Indirect Indirect materials require phonons to tunnel, thus reducing the probability of a tunneling event Tunnel Current Expressions m*1/ 2 EG3 / 2 2 Et exp T exp E 2 2eF E 4 2eF *

3 m EG 4 2m *E g q m * Va Jt exp( 1 / 2 2 2 3q 4 2 E g 3 1/ 2 3/ 2 ) 1 dVeff B d 1

S ln10( 2 ) Veff dVgs dVgs Lateral TFET Proposed by our own Qin Zhang Can theoretically beat 60 mV/decade subthreshold swing G S x ox y p+ Si L tox W

BOX n+ Si tSi D Lateral TFET Off State On State Another Lateral TFET Proposed by A. Zaslavsky in SOI, although original idea from Shockley Gate placed on top of depletion region GATE N+ P+

OX Si More about AZ TFET Double Lateral TFET Acts as back-to-back TD pair at 0 gate bias Gate bias of either polarity will break tunneling condition GATE N+ P+ OX Si N+

Fabrication Techniques As mentioned earlier, heavily-doped, abrupt junctions are needed Can be obtained using several different methods Ion implantation Rapid thermal diffusion Molecular beam epitaxy Laser diffusion Doping by Rapid Thermal Processor Approach: Rapid thermal diffusion Spin-on diffusants 100 mm wafers IC-compatible processes Modular Process Technology RTP-600S

Proximity Rapid Thermal Diffusion Rapid Thermal Diffusion Phosphorus ERFC tail -12 10 -13 -2 D (cm /s) 10 -14

10 Gaussian tail Athena defaults -15 10 Gaussian peak -16 10 D = D.0*exp[-D.E/(kT)] -17 10

800 040712DPfit.QCP 900 1000 Temperature ( C) 1100 Transient-enhanced diffusion effects dominate, increasing diffusivity of dopants Ion Implantation 22 cut line -3 Active Concentration (cm )

10 1021 phos. net 1020 1 nm/decade at junction boron 1 keV implants: -2 B: 1.6e15 cm -2 19 P: 1e15 cm 10

0 040915lateraldop01.qpc anneal: 800 C spike 0.2 0.4 0.6 0.8 Horizontal Position (m) 1 Simulated Built-in Field 6 3.0 10 6 Electric Field (V/cm)

2.5 10 6 average E-field: 2.41e6 V/cm 2.0 10 1.5 106 calculated peak tunnel current: 2 20.2 kA/cm 6

1.0 10 5 5.0 10 0.0 -5.0 105 0 040915efield01.qpc 0.2 0.4 0.6 0.8 Horizontal Position (m) 1 Simulated Band Diagram 1.5

Energy (eV) 1 tunneling distance: 6 nm 0.5 0 E C -0.5 -1 E V

-1.5 0 040915band01.qpc 0.2 0.4 0.6 0.8 Horizontal Position (m) 1 First TDs from Rapid Thermal Diffusion Temperature Dependence -8 1 10

Peak-to-Valley Current Ratio: 1.22 -9 Al p+ Si, B-diffusion n+ Si, P-diffusion n+ Si substrate, P-doped 2a0716 Current (A) 8 10 2 Peak Current Density: 30.85 A/cm 25 C 0 C -25 C -9

6 10 -9 4 10 device area: 150 m diameter -9 2 10 0 0 0.2 0.4

0.6 Voltage (V) 0.8 1 Wafer: W22 TDs with Oxide Window Process 0.3 2 J = 266 A/cm p PVR = 2.15 Current (mA)

First demonstration of tunnel diodes on high resistivity 1 5 k cm substrates 0.2 0.1 0 High resistivity substrate 1-5 k cm -0.1 Enables microwave characterization

-0.2 -0.2 Y140, (5,3)(2,1), 4 x 16 m 0 0.2 0.4 Voltage (V) 0.6 2 0.8 Conclusions Tunnel diodes are expected to add

another node in the road Three-terminal tunnel devices could add several nodes at the end of CMOS-scaling Challenges facing TFETs are more practical than theoretical Lithography, SOI process optimization