Welcome to the ECE 449 Computer Design Lab

Welcome to the ECE 449 Computer Design Lab

Lecture 2 VHDL Refresher ECE 448 FPGA and ASIC Design with VHDL George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 1, Gate-Level Combinational Circuit Recommended S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 2.10, Introduction to VHDL ECE 448 FPGA and ASIC Design with VHDL

2 Recommended reading Wikipedia The Free On-line Encyclopedia VHDL - http://en.wikipedia.org/wiki/VHDL Verilog - http://en.wikipedia.org/wiki/Verilog ECE 448 FPGA and ASIC Design with VHDL 3 Brief History of VHDL ECE 448 FPGA and ASIC Design with VHDL 4 VHDL VHDL is a language for describing digital

hardware used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language ECE 448 FPGA and ASIC Design with VHDL 5 Genesis of VHDL State of art circa 1980 Multiple design entry methods and hardware description languages in use No or limited portability of designs between CAD tools from different vendors Objective: shortening the time from a design concept to implementation from 18 months to 6 months

ECE 448 FPGA and ASIC Design with VHDL 6 A Brief History of VHDL July 1983: a DoD contract for the development of VHDL awarded to Intermetrics IBM Texas Instruments August 1985: VHDL Version 7.2 released December 1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard ECE 448 FPGA and ASIC Design with VHDL 7

Subsequent versions of VHDL IEEE-1076 1987 IEEE-1076 1993 most commonly supported by CAD tools IEEE-1076 2000 (minor changes) IEEE-1076 2002 (minor changes) IEEE-1076 2008 supported by the new generation of CAD tools, such as Xilinx Vivado 8 Verilog ECE 448 FPGA and ASIC Design with VHDL 9

Verilog Essentially identical in function to VHDL Simpler and syntactically different C-like Gateway Design Automation Co., 1985 Gateway acquired by Cadence in 1990 IEEE Standard 1364-1995 (Verilog-95) Early de facto standard for ASIC design Subsequent versions Verilog 2001 (major extensions) dominant version used in industry Verilog 2005 (minor changes) SystemVerilog (IEEE Standards 1800-2009, 1800-2017) (new features and capabilities aiding design verification and design modeling) Programming language interface to allow connection to non-Verilog code 10

VHDL vs. Verilog Government Developed Commercially Developed Ada based C based Strongly Type Cast

Mildly Type Cast Case-insensitive Case-sensitive Difficult to learn Easier to Learn More Powerful Less Powerful ECE 448 FPGA and ASIC Design with VHDL 11 How to learn Verilog by yourself ?

12 How to learn Verilog by yourself ? 13 Features of VHDL and Verilog Technology/vendor independent Portable Reusable ECE 448 FPGA and ASIC Design with VHDL 14 VHDL Fundamentals ECE 448 FPGA and ASIC Design with VHDL

15 Naming and Labeling (1) VHDL is case insensitive Example: Names or labels databus Databus DataBus DATABUS are all equivalent ECE 448 FPGA and ASIC Design with VHDL 16 Naming and Labeling (2) General rules of thumb (according to VHDL-87)

1. 2. 3. 4. 5. All names should start with an alphabet character (a-z or A-Z) Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.) Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid) All names and labels in a given entity and architecture must be unique ECE 448 FPGA and ASIC Design with VHDL

17 Extended Identifiers Allowed only in VHDL-93 and higher: 1. 2. 3. 4. 5. Enclosed in backslashes May contain spaces and consecutive underscores May contain punctuation and reserved characters within a name (!, ?, ., &, +, -, etc.) VHDL keywords allowed Case sensitive Examples: \rdy\

\RDY\ \My design\ \my design\ ECE 448 FPGA and ASIC Design with VHDL \!a\ \-a\ 18 Free Format VHDL is a free format language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then

or if (a=b) then or if (a = b) then are all equivalent ECE 448 FPGA and ASIC Design with VHDL 19 Readability standards & coding style Adopt readability standards based on one of the

the two main textbooks: Chu or Brown/Vranesic Use coding style recommended in OpenCores Coding Guidelines linked from the course web page Strictly enforced by the lab instructors and myself. Penalty points may be enforced for not following these recommendations!!! ECE 448 FPGA and ASIC Design with VHDL 20 Comments Comments in VHDL are indicated with a double dash, i.e., -- Comment indicator can be placed anywhere in the line Any text that follows in the same line is treated as a comment

Carriage return terminates a comment No method for commenting a block extending over a couple of lines (VHDL-2008 allows using /* */) Examples: -- main subcircuit Data_in <= Data_bus; -- reading data from the input FIFO ECE 448 FPGA and ASIC Design with VHDL 21 Comments Explain the function of module to other designers Explanatory, not just restatement of code Dont explain bad code rewrite it! Locate close to code described Put near executable code, not just in a header Express yourself in code, not in comments Minimize duplicate information

ECE 448 FPGA and ASIC Design with VHDL 22 Design Entity ECE 448 FPGA and ASIC Design with VHDL 23 Example: NAND Gate a z b ECE 448 FPGA and ASIC Design with VHDL a

0 0 1 1 b 0 1 0 1 z 1 1 1 0 24

Example VHDL Code 3 sections to a piece of VHDL code File extension for a VHDL file is .vhd Name of the file should be the same as the entity name (nand_gate.vhd) [OpenCores Coding Guidelines] LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY DECLARATION ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate;

ENTITY DECLARATION ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model; ARCHITECTURE BODY ECE 448 FPGA and ASIC Design with VHDL 25 Design Entity design entity entity declaration architecture 1

Design Entity - most basic building block of a design. One entity can have many different architectures. architecture 2 architecture 3 ECE 448 FPGA and ASIC Design with VHDL 26 Entity Declaration Entity Declaration describes an interface of the component, i.e. input and output ports. Entity name Port names

Port type ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; Reserved words Semicolon No Semicolon after last port

Port modes (data flow directions) ECE 448 FPGA and ASIC Design with VHDL 27 Entity declaration simplified syntax ENTITY entity_name IS PORT ( port_name : port_mode signal_type; port_name : port_mode signal_type; . port_name : port_mode signal_type); END entity_name; ECE 448 FPGA and ASIC Design with VHDL

28 Port Mode IN Port signal Entity a Driver resides outside the entity ECE 448 FPGA and ASIC Design with VHDL 29 Port Mode OUT Entity Port signal

z c Driver resides inside the entity ECE 448 FPGA and ASIC Design with VHDL In VHDL-93, an output cannot be read within the entity. This limitation removed in VHDL-2008. c <= z 30 Port Mode OUT (with extra signal)

Entity Port signal x c Driver resides inside the entity ECE 448 FPGA and ASIC Design with VHDL z Signal X can be read inside the entity z <= x c <= x 31

Port Mode INOUT Entity Port signal a Signal can be read inside the entity Driver may reside both inside and outside of the entity ECE 448 FPGA and ASIC Design with VHDL 32 Architecture (Architecture body)

Describes an implementation of a design entity Architecture example: ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow; ECE 448 FPGA and ASIC Design with VHDL 33 Architecture simplified syntax ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code

END architecture_name; ECE 448 FPGA and ASIC Design with VHDL 34 Entity Declaration & Architecture nand_gate.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate;

ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow; ECE 448 FPGA and ASIC Design with VHDL 35 Tips & Hints Place each entity in a different file. The name of each file should be exactly the same as the name of an entity it contains. These rules are not enforced by all tools but are worth following in order to increase readability and portability of your designs

ECE 448 FPGA and ASIC Design with VHDL 36 Tips & Hints Place the declaration of each port, signal, constant, and variable in a separate line These rules are not enforced by all tools but are worth following in order to increase readability and portability of your designs ECE 448 FPGA and ASIC Design with VHDL 37 Libraries

ECE 448 FPGA and ASIC Design with VHDL 38 Library Declarations LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; Library declaration

Use all definitions from the package std_logic_1164 ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow; ECE 448 FPGA and ASIC Design with VHDL 39 Library declarations - syntax LIBRARY library_name; USE library_name.package_name.package_parts; ECE 448 FPGA and ASIC Design with VHDL

40 Fundamental parts of a library LIBRARY PACKAGE 1 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS ECE 448 FPGA and ASIC Design with VHDL PACKAGE 2 TYPES CONSTANTS FUNCTIONS PROCEDURES

COMPONENTS 41 Libraries ieee Specifies multi-level logic system, including STD_LOGIC, and STD_LOGIC_VECTOR data types Need to be explicitly declared std Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.

Visible by default work Holds current designs after compilation ECE 448 FPGA and ASIC Design with VHDL 42 STD_LOGIC Demystified ECE 448 FPGA and ASIC Design with VHDL 43 STD_LOGIC LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS

PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow; What is STD_LOGIC you ask? ECE 448 FPGA and ASIC Design with VHDL 44 BIT versus STD_LOGIC

BIT type can only have a value of '0' or '1' STD_LOGIC can have nine values 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' Useful mainly for simulation '0', '1', 'Z', '-' are synthesizable (your codes should contain only these four values) 45 STD_LOGIC type demystified Value Meaning U Uninitialized X Forcing (Strong driven) Unknown

0 Forcing (Strong driven) 0 1 Forcing (Strong driven) 1 Z High Impedance W Weak (Weakly driven) Unknown L

Weak (Weakly driven) 0. Models a pull down. H Weak (Weakly driven) 1. Models a pull up. - Don't Care 46 More on STD_LOGIC Meanings (1) '1' 'X'

Contention on the bus X '0' ECE 448 FPGA and ASIC Design with VHDL 47 More on STD_LOGIC Meanings (2) ECE 448 FPGA and ASIC Design with VHDL 48 More on STD_LOGIC Meanings (3) VDD VDD 'H'

'0' '1' 'L' ECE 448 FPGA and ASIC Design with VHDL 49 More on STD_LOGIC Meanings (4) - Do not care. Can be assigned to outputs for the case of invalid inputs (may produce significant improvement in resource utilization after synthesis). Must be used with great caution. For example in VHDL-93, the direct comparison 1 = -

gives FALSE. The "std_match" functions defined in the numeric_std package must be used to make this value work as expected: Example: if (std_match(address, "-11---") then ... elsif (std_match(address, "-01---") then ... else ... end if; ECE 448 FPGA and ASIC Design with VHDL 50 Resolving logic levels U X 0 1

Z W L H - U U U U U U U U U U X U

X X X X X X X X 0 U X 0 X 0 0 0 0 X

1 U X X 1 1 1 1 1 X Z U X 0 1 Z W

L H X W U X 0 1 W W W W X L U X 0

1 L W L W X H U X 0 1 H W W H X U

X X X X X X X X 51 STD_LOGIC Rules In ECE 448, use std_logic or std_logic_vector for all entity input or output ports Do not use integer, unsigned, signed, bit for ports You can use them inside of architectures if desired You can use them in generics

Instead use std_logic_vector and a conversion function inside of your architecture [Consistent with OpenCores Coding Guidelines] ECE 448 FPGA and ASIC Design with VHDL 52 Modeling Wires and Buses ECE 448 FPGA and ASIC Design with VHDL 53 Signals SIGNAL a : STD_LOGIC; a 1

wire SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); b 8 bus ECE 448 FPGA and ASIC Design with VHDL 54 Standard Logic Vectors SIGNAL a: STD_LOGIC; SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0);

. a <= 1; b <= "0000"; -- Binary base assumed by default c <= B"0000"; -- Binary base explicitly specified d <= X"AF67"; -- Hexadecimal base e <= O"723"; -- Octal base ECE 448 FPGA and ASIC Design with VHDL 55 Vectors and Concatenation SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= "0000"; b <= "1111"; c <= a & b; -- c = "00001111" d <= '0' & "0001111"; -- d <= "00001111" e <= '0' & '0' & '0' & '0' & '1' & '1' & '1' & '1'; -- e <= "00001111" ECE 448 FPGA and ASIC Design with VHDL 56 Types of VHDL Description

(Modeling Styles) ECE 448 FPGA and ASIC Design with VHDL 57 Types of VHDL Description: Convention used in this class VHDL Descriptions Testbenches dataflow Concurrent statements structural Components and interconnects

behavioral Sequential statements Registers State machines Decoders Subset most suitable for synthesis ECE 448 FPGA and ASIC Design with VHDL 58 Types of VHDL Description: Alternative convention VHDL Descriptions Behavioral Structural Components & interconnects

ECE 448 FPGA and ASIC Design with VHDL dataflow Concurrent statements algorithmic Sequential statements 59 xor3 Example ECE 448 FPGA and ASIC Design with VHDL 60

Entity xor3_gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor3_gate IS PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC ); end xor3_gate; ECE 448 FPGA and ASIC Design with VHDL 61 Dataflow Architecture (xor3_gate) ARCHITECTURE dataflow OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC; BEGIN

U1_OUT <= A XOR B; Result <= U1_OUT XOR C; END dataflow; U1_OUT ECE 448 FPGA and ASIC Design with VHDL 62 Dataflow Description Describes how data moves through the system and the various processing steps. Dataflow uses series of concurrent statements to realize logic. Dataflow is most useful style when series of Boolean equations can represent a logic used to implement simple combinational logic Dataflow code also called concurrent code Concurrent statements are evaluated at the same time; thus, the order of these statements doesnt matter

This is not true for sequential/behavioral statements This order U1_out <= A XOR B; Result <= U1_out XOR C; Is the same as this order Result <= U1_out XOR C; U1_out <= A XOR B; ECE 448 FPGA and ASIC Design with VHDL 63 Structural Architecture in VHDL 93 A B C ARCHITECTURE structural OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC; BEGIN

U1: entity work.xor2(dataflow) PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: entity work.xor2(dataflow) PORT MAP (I1 => U1_OUT, I2 => C, Y => Result); END structural; I1 I2 xor3_gate Result U1_OUT Y

I1 I2 Y PORT NAME LOCAL WIRE NAME ECE 448 FPGA and ASIC Design with VHDL 64 xor2 xor2.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor2 IS PORT(

I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC); END xor2; ARCHITECTURE dataflow OF xor2 IS BEGIN Y <= I1 xor I2; END dataflow; ECE 448 FPGA and ASIC Design with VHDL 65 Structural Architecture in VHDL 87 ARCHITECTURE structural OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC;

COMPONENT xor2 PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: xor2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: xor2 PORT MAP (I1 => U1_OUT, I2 => C, Y => Result); END structural; ECE 448 FPGA and ASIC Design with VHDL A

B C I1 I2 xor3_gate Result U1_OUT Y I1 I2 Y PORT NAME

LOCAL WIRE NAME 66 Structural Description Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components. Structural style is useful when expressing a design that is naturally composed of sub-blocks. ECE 448 FPGA and ASIC Design with VHDL 67

Behavioral Architecture (xor3 gate) ARCHITECTURE behavioral OF xor3 IS BEGIN xor3_behave: PROCESS (A, B, C) BEGIN IF ((A XOR B XOR C) = '1') THEN Result <= '1'; ELSE Result <= '0'; END IF; END PROCESS xor3_behave; END behavioral; ECE 448 FPGA and ASIC Design with VHDL 68 Behavioral Description It accurately models what happens on the inputs and outputs of the black box (no matter what is

inside and how it works). This style uses PROCESS statements in VHDL. ECE 448 FPGA and ASIC Design with VHDL 69 ? ECE 448 FPGA and ASIC Design with VHDL 70

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